MAX1027BEEE-T Maxim Integrated, MAX1027BEEE-T Datasheet
MAX1027BEEE-T
Specifications of MAX1027BEEE-T
Related parts for MAX1027BEEE-T
MAX1027BEEE-T Summary of contents
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... Scan Mode, Internal Averaging, and Internal Clock o Low-Power Single +3V Operation 1mA at 300ksps o Internal 2.5V Reference or External Differential Reference o 10MHz 3-Wire SPI/QSPI/MICROWIRE-Compatible Interface o Space-Saving 28-Pin 5mm x 5mm TQFN Package PART MAX1027BCEE+T MAX1027BEEE+T MAX1029BCEP+T MAX1029BEEP+T + Denotes a lead(Pb)-free/RoHS-compliant package Tape and reel. Ordering Information continued at end of data sheet. 16 EOC 15 DOUT ...
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ADCs with FIFO, Temp Sensor, Internal Reference ABSOLUTE MAXIMUM RATINGS V to GND ..............................................................-0.3V to +6V DD CS, SCLK, DIN, EOC, DOUT to GND.........-0. AIN0–AIN13, REF-/AIN_, CNVST/AIN_, REF+ to GND.........................................-0. Maximum Current into Any ...
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ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V 300kHz SAMPLE noted. Typical values are +25°C.) A PARAMETER SYMBOL CONVERSION RATE Power-Up Time Acquisition Time Conversion Time t External Clock Frequency Aperture Delay Aperture ...
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ADCs with FIFO, Temp Sensor, Internal Reference ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V 300kHz SAMPLE noted. Typical values are +25°C.) A PARAMETER SYMBOL DIGITAL INPUTS (SCLK, DIN, CS, CNVST) ...
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TIMING CHARACTERISTICS (Figure 1) PARAMETER SYMBOL SCLK Clock Period SCLK Duty Cycle SCLK Fall to DOUT Transition CS Rise to DOUT Disable CS Fall to DOUT Enable DIN to SCLK Rise Setup SCLK Rise to DIN Hold CS Fall to ...
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ADCs with FIFO, Temp Sensor, Internal Reference (V = +3V +2.5V 4.8MHz REF SCLK SFDR vs. FREQUENCY 100 100 1k FREQUENCY (kHz) SUPPLY CURRENT vs. ...
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V = +2.5V 4.8MHz REF SCLK OFFSET ERROR vs. SUPPLY VOLTAGE 0.70 0.65 0.60 0. 300ksps SAMPLE 0.50 3.0 3.3 2.7 V (V) DD GAIN ERROR vs. TEMPERATURE 0 ...
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ADCs with FIFO, Temp Sensor, Internal Reference MAX1031 MAX1031 MAX1029 MAX1027 TQFN QSOP 2–12, 26, 1–14 — 27, 28 — — 1–10 — — — — — — 11 — — — — — ...
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CS t CSS0 t CL SCLK DIN t DOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK CNVST AIN1 AIN2 AIN15 REF- REF+ Figure 2. Functional Diagram _______________________________________________________________________________________ 10-Bit 300ksps ADCs with FIFO, Temp ...
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ADCs with FIFO, Temp Sensor, Internal Reference Detailed Description The MAX1027/MAX1029/MAX1031 are low-power, seri- al-output, multichannel ADCs with temperature-sensing capability for temperature-control, process-control, and monitoring applications. These 10-bit ADCs have inter- nal track and hold (T/H) circuitry that ...
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REF AIN0-AIN15 DAC GND (SINGLE ENDED); AIN0, AIN2, AIN4…AIN14 CIN+ (DIFFERENTIAL) HOLD GND CIN- (SINGLE ENDED); AIN1, AIN3, AIN5…AIN15 HOLD (DIFFERENTIAL Figure 3. Equivalent Input Circuit In differential mode, the T/H samples the difference between two analog ...
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ADCs with FIFO, Temp Sensor, Internal Reference temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement ...
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Table 2. Conversion Register* BIT BIT FUNCTION NAME — 7 (MSB) Set select conversion register. CHSEL3 6 Analog input channel select. CHSEL2 5 Analog input channel select. CHSEL1 4 Analog input channel select. CHSEL0 3 Analog input ...
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ADCs with FIFO, Temp Sensor, Internal Reference Table 3. Setup Register* BIT NAME BIT — 7 (MSB) Set to zero to select setup register. — 6 Set select setup register. Clock mode and CNVST configuration. ...
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Select scan mode 10 to scan the same channel multiple times. Clock mode 11 disables averaging. Write to the reset register (as shown in Table 7) to clear the FIFO or to reset all registers to their ...
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ADCs with FIFO, Temp Sensor, Internal Reference Table 6. Averaging Register* BIT NAME BIT — 7 (MSB) Set to zero to select averaging register. — 6 Set to zero to select averaging register. — 5 Set to 1 ...
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Internally Timed Acquisitions and Conversions Using CNVST Performing Conversions in Clock Mode 00 In clock mode 00, the wake up, acquisition, conversion, and shutdown sequences are initiated through CNVST and performed automatically using the internal oscilla- tor. Results are added ...
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ADCs with FIFO, Temp Sensor, Internal Reference CNVST (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN CS SCLK DOUT EOC THE ...
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DIN (ACQUISITION1) CS SCLK DOUT EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 clock. Scanning and averaging are disabled, and the conversion result is available at DOUT during the con- version. See Figure 7 ...
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ADCs with FIFO, Temp Sensor, Internal Reference OUTPUT CODE FULL-SCALE TRANSITION 111 110 101 011 010 00 . ...
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TOP VIEW + AIN0 1 AIN1 2 AIN2 3 AIN3 4 MAX1031 AIN4 5 AIN5 6 AIN6 7 AIN7 8 AIN8 9 AIN9 10 AIN10 11 AIN11 12 QSOP Effective Number of Bits Effective number of bits (ENOB) indicates the ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products ...