MAX1415EUE Maxim Integrated, MAX1415EUE Datasheet - Page 9

• Manufacturer Part Number: MAX1415EUE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1415EUE

• Number Of Channels: 2
• Architecture: Sigma-Delta
• Conversion Rate: 0.5 KSPs
• Resolution: 16 bit
• Input Type: Differential
• Snr: No
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-16
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: - 45 C
• Number Of Converters: 1
• Voltage Reference: 1.75 V

TIMING CHARACTERISTICS—MAX1416 (continued)
(Note 16) (Figures 8, 9)
Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 3. This applies after calibration at the given
Note 2: Recalibration at any temperature removes these drift errors.
Note 3: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
Note 4: Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar
Note 5: Gain error does not include zero-scale errors. It is calculated as (full-scale error – unipolar offset error) for unipolar ranges,
Note 6: Gain-error drift does not include unipolar offset drift or bipolar zero drift. Effectively, it is the drift of the part if only zero-
Note 7: The analog input voltage range on AIN+ is given here with respect to the voltage on AIN- on the MAX1415/MAX1416.
Note 8: This common-mode voltage range is allowed, provided that the input voltage on the analog inputs does not go more posi-
Note 9: The REF differential voltage, V
Note 10: Guaranteed by design.
Note 11: These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed (V
Note 12: When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the supply
Note 13: If the external master clock continues to run in power-down mode, the power-down current typically increases to 67µA at
Note 14: Measured at DC and applied in the selected passband. PSRR at 50Hz exceeds 120dB with filter notches of 25Hz or 50Hz.
Note 15: Provide f
Note 16: All input signals are specified with t
DIN to SCLK Setup Time
DIN to SCLK Hold Time
temperature.
and bipolar input ranges.
input ranges.
and (full-scale error – bipolar zero error) for bipolar ranges.
scale calibrations are performed.
tive than (V
but with increased leakage at high temperature.
30mV) or go more negative than (GND - 30mV). The offset-calibration limit applies to both the unipolar zero point and the
bipolar zero point.
current and power dissipation varies depending on the crystal or resonator type. Supply current is measured with the digi-
tal inputs connected to 0 or V
3V. When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the
clock generator continues to run in power-down mode and the power dissipation depends on the crystal or resonator type
(see the Power-Down Modes section).
PSRR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz.
PSRR depends on both gain and V
higher-than-specified current and can possibly become uncalibrated.
PARAMETER
8 to 128
GAIN
CLKIN
1
2
4
_______________________________________________________________________________________
DD
+ 30mV) or more negative than (GND - 30mV). Parts are functional with voltages down to (GND - 200mV),
whenever the MAX1415/MAX1416 are not in power-down mode. If no clock is present, the device can draw
PSRR (V
SYMBOL
DD
REF
90
78
84
91
t
t
10
, CLKIN connected to an external clock source, and CLKDIS = 1.
9
DD
, is the voltage on REF+ referenced to REF- (V
DD
r
= 5V)
= t
.
f
16-Bit, Low-Power, 2-Channel,
= 5ns (10% to 90% of V
PSRR (V
(dB)
86
78
85
93
DD
CONDITIONS
= 3V)
DD
) and timed from a voltage level of 1.6V.
Sigma-Delta ADCs
REF
= V
REF+
MIN
30
20
- V
REF-)
TYP
.
MAX
UNITS
ns
ns
DD
+
9