MAX1203BEPP Maxim Integrated, MAX1203BEPP Datasheet - Page 6

• Manufacturer Part Number: MAX1203BEPP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1203BEPP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TIMING CHARACTERISTICS
(V
6
Note 1: Tested at V
Note 2:
Note 3: MAX1202—internal reference, offset nulled; MAX1203—external reference (V
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
Note 11: Measured at V
Note 12: Measured at VL = 2.7V and VL = 3.6V.
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
(Note 6)
CS Rise to SSTRB Output
Disable (Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
DD
_______________________________________________________________________________________
= +5V ±5%, VL = 2.7V to 3.6V, V
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
REFADJ = GND. Shutdown supply current is also dependent on V
active (CS low), the logic supply current depends on f
PARAMETER
DD
SUPPLY
= 5.0V; V
+ 5% and V
SS
= 0V; unipolar-input mode.
SYMBOL
SS
t
SSTRB
t
t
t
t
t
t
ACQ
t
t
t
t
CSH
t
SCK
t
CSS
t
SDV
STR
DO
= 0V or -5V ±5%, T
DS
DH
DV
CH
TR
CL
SUPPLY
C
C
C
C
External-clock mode only, C
External-clock mode only, C
Internal-clock mode only
LOAD
LOAD
LOAD
LOAD
- 5% only.
= 100pF
= 100pF
= 100pF
= 100pF
SS
A
to V
= T
CONDITIONS
SCLK
MIN
DD
.
, and on the static and capacitive load at DOUT and SSTRB.
to T
MAX
IH
, unless otherwise noted.)
LOAD
LOAD
(Figure 12c).
= 100pF
= 100pF
REF
= 4.096V), offset nulled.
MIN
100
100
200
200
1.5
20
0
0
TYP
MAX
240
240
240
240
240
240
0
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns