M4A3-128/64-10CAC Lattice, M4A3-128/64-10CAC Datasheet - Page 9

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M4A3-128/64-10CAC

Manufacturer Part Number
M4A3-128/64-10CAC
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet

Specifications of M4A3-128/64-10CAC

Product Category
CPLD - Complex Programmable Logic Devices
Memory Type
EEPROM
Number Of Macrocells
128
Maximum Operating Frequency
100 MHz
Delay Time
5 ns
Number Of Programmable I/os
400
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
CABGA-100-400
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
920
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M4A3-128/64-10CAC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed away;
e. Extended cluster routed away
single-product-term, active high
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed away;
e. Extended cluster routed away
single-product-term, active high
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All
configurations have the same delay. This means that designers do not have to decide between optimizing
resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide
XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-flop to provide
for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra
product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the
flexibility to route product terms elsewhere without giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of
the block have fewer product terms available.
ispMACH 4A Family
9

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