MAX1245BEAP-T Maxim Integrated, MAX1245BEAP-T Datasheet - Page 13

• Manufacturer Part Number: MAX1245BEAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1245BEAP-T

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.375 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.048 V

selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provid-
ed that the minimum acquisition time, t
above 2.0µs.
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
SSTRB • • •
SCLK • • •
DOUT • • •
CS • • •
SSTRB
DOUT
SCLK
A/D STATE
DIN
CS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
START
______________________________________________________________________________________
1
SEL2 SEL1 SEL0 UNI/
PD0 CLOCK IN
2
3
IDLE
4
t
CSH
BIP
5
(SCLK = 1.5MHz)
SGL/
DIF
ACQUISITION
6
Data Framing
2.0µs
+2.375V, Low-Power, 8-Channel,
PD1
7
t
SSTRB
ACQ
PD0
8
, is kept
(SHDN = OPEN)
CONVERSION
7.5µs MAX
t
CONV
t
CONV
9
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated,
and a new one is started.
MSB B10
B11
IDLE
10
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
11
B9
12
Serial 12-Bit ADC
t
SCK
18
B2
19
B1
20
LSB
B0
OR
21
FILLED WITH
ZEROS
t
CSS
22
23
24
DD
t
DO
is applied.
13