M4-96/96-20YI Lattice, M4-96/96-20YI Datasheet - Page 10

• Manufacturer Part Number: M4-96/96-20YI
• Description: CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of M4-96/96-20YI

• Product Category: CPLD - Complex Programmable Logic Devices
• Number Of Macrocells: 96
• Delay Time: 20 nS
• Number Of Programmable I/os: 400
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package / Case: PQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 24

Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
10
From Logic Allocator
From PAL-Block
Clock Generator
Individual Clock
Product Terms
Product Term
Product Term
Initialization
Initialization
From Logic
PAL-Clock
Individual macrocell resources
PAL-Block
Generator
Common PAL-block resource
Individual
Allocator
From
Power-Up
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Block CLK0
Block CLK1
Power-Up
Reset
Reset
ispMACH 4A Family
a. Synchronous mode
b. Asynchronous mode
Figure 5. Macrocell
SWAP
SWAP
D/T/L
D/T/L
AP
AP
AR
AR
Q
Q
To Output and Input
Switch Matrices
To Output and Input
Switch Matrices
17466G-009
17466G-010