MAX187BMJA Maxim Integrated, MAX187BMJA Datasheet - Page 13

• Manufacturer Part Number: MAX187BMJA
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX187BMJA

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 75 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Package / Case: CDIP N
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 55 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The effective resolution (effective number of bits) the
ADC provides can be determined by transposing the
above equation and substituting in the measured SINAD:
N = (SINAD - 1.76)/6.02. Figure 12 shows the effective
number of bits as a function of the input frequency for the
MAX187/MAX189.
If a pure sine wave is sampled by an ADC at greater than
the Nyquist frequency, the nonlinearities in the ADC’s
transfer function create harmonics of the input frequency
present in the sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all the harmonics (in the frequency band above
DC and below one-half the sample rate, but not including
the DC component) to the RMS amplitude of the funda-
mental frequency. This is expressed as follows:
where V
through V
Nth harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th harmonics.
Figure 12. Effective Bits vs. Input Frequency
Maxim Integrated
THD 20log
1
N
is the fundamental RMS amplitude, and V
12.2
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
=
are the amplitudes of the 2nd through
1
V
Total Harmonic Distortion
2
INPUT FREQUENCY (kHz)
2
10
+
V
3
2
+
(UNDERSAMPLED)
V
V
1
+5V, Low-Power, 12-Bit Serial ADCs
4
100
2
+ …
V
N
1000
2
2
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and MICROWIRE standard serial inter-
faces.
If a serial interface is available, set the CPU’s serial inter-
face in master mode so the CPU generates the serial
clock. Choose a clock frequency up to 2.5MHz.
1) Use a general-purpose I/O line on the CPU to pull CS
2) Wait the for the maximum conversion time specified
3) Activate SCLK for a minimum of 13 clock cycles.
4) Pull CS high at or after the 13th falling clock edge. If
5) With CS = high, wait the minimum specified time, t
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of the
conversion padded with one leading 1, and trailing 0s if
SCLK is still active with CS kept low.
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion in progress. Wait until DOUT
goes high or the maximum specified 8.5Fs conversion
time. Two consecutive 1-byte reads are required to get
the full 12 bits from the ADC. DOUT output data transi-
tions on SCLK’s falling edge and is clocked into the FP
on SCLK’s rising edge.
The first byte contains a leading 1 and 7 bits of conver-
sion result. The second byte contains the remaining 5
bits and 3 trailing 0s. See Figure 13 for connections and
Figure 14 for timing.
low. Keep SCLK low.
before activating SCLK. Alternatively, look for a DOUT
rising edge to determine the end of conversion.
The first falling clock edge will produce the MSB of
the DOUT conversion. DOUT output data transitions
on SCLK’s falling edge and is available in MSB-first
format. Observe the SCLK to DOUT valid timing char-
acteristic. Data can be clocked into the FP on SCLK’s
rising edge.
CS remains low, trailing zeros are clocked out after
the LSB.
before launching a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversions end, wait for the minimum acquisition
time, t
ACQ
Connection to Standard Interfaces
, before starting a new conversion.
Applications Information
MAX187/MAX189
SPI and MICROWIRE
CS
13
,