MAX126BCAX+ Maxim Integrated, MAX126BCAX+ Datasheet - Page 6

• Manufacturer Part Number: MAX126BCAX+
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX126BCAX+

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: +/- 2.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SSOP-36
• Maximum Power Dissipation: 941 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

The MAX125/MAX126 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
14-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX125/MAX126 internal micro-
sequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (see Figure 2).
The conversion timing and control sequences are
derived from a 16MHz external clock, the CONVST
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
6
______________________________________________________________Pin Description
_______________Detailed Description
_______________________________________________________________________________________
19, 20
21–24
32, 33
34, 35
8, 36
9–16
PIN
1, 2
3, 4
17
18
25
26
27
28
29
30
31
5
6
7
D3/A3–D0/A0
CH2B, CH2A
CH1B, CH1A
CH4A, CH4B
CH3A, CH3B
CONVST
REFOUT
D13–D6
D5, D4
NAME
REFIN
AGND
DGND
DV
AV
AV
CLK
WR
INT
RD
CS
DD
DD
SS
Channel 2 Multiplexed Inputs, single-ended
Channel 1 Multiplexed Inputs, single-ended
+5V ±5% Analog Supply Voltage
External Reference Input/Internal Reference Output. Bypass with a 0.1µF capacitor to AGND.
Reference-Buffer Output. Bypass with a 4.7µF capacitor to AGND.
Analog Ground. Both pins must be tied to ground.
Data Bits. D13 = MSB.
+5V ±5% Digital Supply Voltage
Digital Ground
Data Bits
Bidirectional Data Bits/Address Bits. D0/A0 = LSB.
Clock Input (duty cycle must be 30% to 70%).
Chip-Select Input (active-low)
Write Input (active-low)
Read Input (active-low)
Conversion-Start Input. Rising edge initiates sampling and conversion sequence.
Interrupt Output. Falling edge indicates the end of a conversion sequence.
-5V ±5% Analog Supply Voltage
Channel 4 Multiplexed Inputs, single-ended
Channel 3 Multiplexed Inputs, single-ended
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
FUNCTION
TO OUTPUT
120pF
PIN
1.6mA
1.0mA
1.6V