MAX1112EAP-T Maxim Integrated, MAX1112EAP-T Datasheet - Page 10

• Manufacturer Part Number: MAX1112EAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1112EAP-T

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 50 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 4.096 V or External

+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t
acquired. It is calculated by:
where R
input signal, and t
source impedances below 2.4kΩ do not significantly
affect the AC performance of the ADC.
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Internal protection diodes, which clamp the analog
input to V
swing from (AGND - 0.3V) to (V
Table 3. Control-Byte Format
10
ACQ
7 (MSB)
0 (LSB)
(MSB)
START
BIT 7
______________________________________________________________________________________
, is the minimum time needed for the signal to be
BIT
6
5
4
3
2
1
IN
DD
t
ACQ
= 6.5kΩ, R
and AGND, allow the channel input pins to
= 6 x (R
SGL/DIF
ACQ
UNI/BIP
START
NAME
BIT 6
SEL2
SEL2
SEL1
SEL0
PD1
PD0
S
is never less than 1µs. Note that
S
= the source impedance of the
+ R
IN
The first logic “1” bit after CS goes low defines the beginning of the control byte.
Select which of the input channels are to be used for the conversion (Tables 1 and 2).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode (Table 4).
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage differ-
ence between two channels is measured (Tables 1 and 2).
1 = fully operational, 0 = power-down.
Selects fully operational or power-down mode.
1 = external clock mode, 0 = internal clock mode.
Selects external or internal clock mode.
) x 18pF
DD
BIT 5
SEL1
Input Bandwidth
+ 0.3V) without dam-
Analog Inputs
BIT 4
SEL0
age. However, for accurate conversions near full scale,
the inputs must not exceed V
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
The MAX1112/MAX1113 can be configured for differen-
tial or single-ended inputs with bits 2 and 3 of the con-
trol byte (Table 3). In single-ended mode, analog inputs
are internally referenced to COM with a full-scale input
range from COM to V
tion, set COM to V
In differential mode, choosing unipolar mode sets the
differential input range at 0V to V
mode, the output code is invalid (code zero) when a
negative differential input voltage is applied. Bipolar
mode sets the differential input range to ±V
Note that in this mode, the common-mode input range
includes both supply rails. See Table 4 for input voltage
ranges.
To quickly evaluate the MAX1112/MAX1113’s analog
performance, use the circuit of Figure 5. The
MAX1112/MAX1113 require a control byte to be written
to DIN before each conversion. Tying DIN to +5V feeds
UNI/BIP
BIT 3
DESCRIPTION
SGL/DIF
BIT 2
REFIN
REFIN
/2.
+ COM. For bipolar opera-
DD
BIT 1
PD1
by more than 50mV or
REFIN
Quick Look
. In unipolar
(LSB)
BIT 0
PD0
REFIN
/2.