MAX1204ACPP Maxim Integrated, MAX1204ACPP Datasheet - Page 14

• Manufacturer Part Number: MAX1204ACPP
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1204ACPP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 66 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

CS’s falling edge does not start a conversion on the
MAX1204. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on SCLK’s falling edge after the
eighth bit of the control byte (the PD0 bit) is clocked into
DIN. The start bit is defined as:
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
MAX1204
14
The first high bit clocked into DIN with CS low any-
time the converter is idle; (e.g., after V
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress appears at DOUT.
SSTRB • • •
SCLK • • •
SSTRB
CS • • •
ADC STATE
DOUT
SCLK
DIN
CS
START
1
or
SEL2 SEL1 SEL0
2
IDLE
PD0 CLOCK IN
3
4
UNI/
DIP
t
CSH
5
SGL/
(SCLK = 2MHz)
DIF
ACQUISITION
6
Data Framing
1.5µs
PD1
DD
7
PD0
t
is applied).
SSTRB
8
CONVERSION
10µs MAX
t
CONV
t
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
CONV
9
If a falling edge on CS forces a start bit before B3
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1204 can run is 15 clocks/conversion. Figure 11a
shows the serial-interface timing necessary to perform
a conversion every 15 SCLK cycles in external clock
mode. If CS is low and SCLK is continuous, guarantee
a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
conversion is typically the fastest that a µC can drive
the MAX1204. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
MSB
B9
10
B8
11
B7
12
18
IDLE
t
SCK
LSB
B0
19
S1
20
S0
21
FILLED WITH
ZEROS
22
t
CSS
23
24
Maxim Integrated