MAX199AMDI Maxim Integrated, MAX199AMDI Datasheet - Page 9

• Manufacturer Part Number: MAX199AMDI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX199AMDI

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Interface Type: Parallel
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 762 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.
Even with V
current-limiting that adequately protects the device.
Input data (control byte) and output data are multiplexed
on a three-state parallel interface. This parallel I/O can
easily be interfaced with a µP. CS, WR, and RD control
the write and read operations. CS is the standard chip-
select signal, which enables a µP to address the MAX199
as an I/O port. When high, it disables the WR and RD
inputs and forces the interface into a high-Z state.
Table 4. Channel Selection
Table 1. Control-Byte Format
Table 2. Range and Polarity Selection
D7 (MSB)
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
A2
2, 1, 0
0
0
0
0
1
1
1
1
PD1
BIP
BIT
7, 6
0
0
1
1
5
4
3
DD
A1
= 0V, the input resistive network provides
0
0
1
1
0
0
1
1
A2, A1, A0
ACQMOD
PD1, PD0
_______________________________________________________________________________________
NAME
RNG
PD0
BIP
RNG
D6
0
1
0
1
A0
0
1
0
1
0
1
0
1
These two bits select the clock and power-down modes (Table 3).
0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
Selects the full-scale voltage magnitude at the input (Table 2).
Selects unipolar or bipolar conversion mode (Table 2).
These are address bits for the input mux to select the “on” channel (Table 4).
ACQMOD
Digital Interface
INPUT RANGE (V)
D5
CH0
Multi-Range (±4V, ±2V, +4V, +2V),
0 to V
0 to V
±V
±V
REF/2
REF
REF/2
REF
CH1
RNG
D4
CH2
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 1 shows the control-
byte format.
The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When read-
ing the output data, CS and RD must be low. When
HBEN is low, the lower eight bits are read. When HBEN
is high, the upper four MSBs are available and the out-
put data bits D4–D7 are either set low (in unipolar
mode) or set to the value of the MSB (in bipolar mode)
(Table 5).
Table 3. Clock and Power-Down Selection
PD1 PD0
0
0
1
1
BIP
D3
DESCRIPTION
CH3
0
1
0
1
Normal Operation / External Clock Mode
Normal Operation / Internal Clock Mode
Standby Power-Down (STBYPD); clock mode
is unaffected
Full Power-Down (FULLPD); clock mode is
unaffected
CH4
D2
A2
DEVICE MODE
CH5
D1
A1
Output Data Format
CH6
Input Format
D0 (LSB)
A0
CH7
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