MAX1033BEUP/GG8 Maxim Integrated, MAX1033BEUP/GG8 Datasheet - Page 15

• Manufacturer Part Number: MAX1033BEUP/GG8
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1033BEUP/GG8

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended/Differential
• Snr: 85 dB
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 879 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 2. External Clock-Mode Conversion (Mode 0)
As a result, the analog input impedance is relatively
constant over input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel. For
example, to configure CH2 and CH3 for a ±3 x V
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±3 x V
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
SSTRB
TRACK AND HOLD*
DOUT
SCLK
DIN
CS
ANALOG INPUT
IMPEDANCE
HIGH
**DIN BYTES 2 TO 4 MUST BE DRIVEN TO LOGIC 0 TO OBTAIN A VALID CONVERSION.
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
S
HOLD
______________________________________________________________________________________
C2
C1
C0
Multirange Inputs, Serial 14-Bit ADCs
0
BYTE 1
0
0
0
**
TRACK
t
ACQ
REF
BYTE 2
REF
8- and 4-Channel, ±3 x V
range
f
dif-
SAMPLE
≈ f
SAMPLING INSTANT
SCLK
/ 32
B13
The MAX1032/MAX1033 input-tracking circuitry has a
2MHz small-signal bandwidth. The 2MHz input band-
width makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD
and -SFDR vs. Input Frequency plot in the Typical
Operating Characteristics .
Figure 7 illustrates the software-selectable single-
ended analog input voltage range that produces a valid
digital output. Each analog input channel can be inde-
pendently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
B12
Analog Input Range and Fault Tolerance
B11
B10
BYTE 3
B9
B8
B7
HOLD
B6
B5
B4
Analog Input Bandwidth
B3
B2
BYTE 4
B1
B0
X
X
IMPEDANCE
HIGH
REF
15