MAX1362EUB Maxim Integrated, MAX1362EUB Datasheet - Page 10

• Manufacturer Part Number: MAX1362EUB
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1362EUB

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 150 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: uMAX
• Maximum Power Dissipation: 689.7 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
The MAX1361 (2.7V to 3.6V) and MAX1362 (4.5V to
5.5V) operate from a single supply and consume 670µA
(typ) at sampling rates up to 94.4ksps and 436µA in
monitor mode at 150ksps. The MAX1361 features a
2.048V internal reference and the MAX1362 features a
4.096V internal reference. All devices can be config-
ured for use with an external reference from 1V to V
Bypass V
capacitor for best performance.
The MAX1361/MAX1362 analog-input architecture con-
tains an analog-input multiplexer (MUX), fully differential
T/H, comparator, and a fully differential switched
capacitive digital-to-analog converter (DAC). Figure 3
shows the equivalent input circuit for the MAX1361/
MAX1362.
In single-ended mode, the analog-input MUX connects
C
GND (see the Configuration/Setup Bytes (Write Cycle)
section). In differential mode, the analog-input MUX
connects C
selected by CS[3:0].
During the acquisition interval, the T/H switches are in
the track position, and C
signal. At the end of the acquisition interval, the T/H
switches move to the hold position, retaining the charge
on C
During the conversion, a switched capacitive DAC
adjusts to restore the comparator input voltage to 0V
within the limits of 10-bit resolution. This action requires
Figure 3. Equivalent Input Circuit
10
T/H
T/H
______________________________________________________________________________________
between the analog input selected by CS[3:0] and
as a stable sample of the input signal.
DD
T/H
to GND using a 0.1µF or greater ceramic
to the plus and minus analog inputs
Analog Input and Track/Hold
AIN3/REF
AIN0
AIN1
AIN2
T/H
charges to the analog-input
ANALOG INPUT MUX
Power Supply
DD
.
C
C
T/H
T/H
10 conversion clock cycles and is equivalent to trans-
ferring a charge of 11pF x (V
binary-weighted capacitive DAC, forming a digital rep-
resentation of the analog-input signal.
Use a low source impedance to ensure an accurate
sample. A source impedance of up to 1.5kΩ does not
significantly degrade sampling accuracy. For larger
source impedances, connect a 100pF capacitor from
the analog input to GND or buffer the input.
In internal clock mode, the T/H circuitry enters track
mode on the eighth rising clock edge of the address
byte (see the Slave Address section). The T/H circuitry
enters hold mode on the falling clock edge of the
acknowledge bit of the address byte (the ninth clock
pulse). The conversions are then internally clocked, dur-
ing which time the MAX1361/MAX1362 hold SCL low.
In external clock mode, the T/H circuitry enters track
mode after a valid address on the rising edge of the
clock during the read bit (R/W = 1, bit 8). Hold mode is
entered on the rising edge of the second clock pulse
during the shifting out of the 1st byte of the result. The
next 10 clock cycles perform the conversions (see
Figure 13).
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition-time constant lengthens and more time
must be allowed between conversions. The acquisition
time (t
to be acquired. It is calculated by:
ACQ
V
) is the minimum time needed for the signal
t
DD
ACQ
/2
REF
REF
≥ 7 x (R
CAPACITIVE
DAC
CAPACITIVE
DAC
SOURCE
IN
MAX1361
MAX1362
+ - V
+ R
IN
IN
-) from C
) x C
IN
T/H
to the