MAX1124EGK-TD Maxim Integrated, MAX1124EGK-TD Datasheet - Page 14

• Manufacturer Part Number: MAX1124EGK-TD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1124EGK-TD

• Number Of Channels: 1
• Architecture: Pipeline
• Conversion Rate: 250000 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 57.1 dB
• Interface Type: LVDS, Parallel
• Operating Supply Voltage: 1.7 V to 1.9 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN EP
• Maximum Power Dissipation: 657 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
determined resistor value between REFADJ and REFIO
increases the full-scale range of the data converter.
Figure 6 shows the two possible configurations and
their impact on the overall full-scale range adjustment
of the MAX1124. Do not use resistor values of less than
13kΩ to avoid instability of the internal gain regulation
loop for the bandgap reference.
The preferred method of clocking the MAX1124 is differ-
entially with LVDS- or PECL-compatible input levels. To
accomplish this, a 50Ω reverse-terminated clock signal
source with low phase noise is AC-coupled into a fast
differential receiver such as the MC100LVEL16 (Figure
7). The receiver produces the necessary PECL output
levels to drive the clock inputs of the data converter.
An RF transformer provides an excellent solution to
convert a single-ended source signal to a fully differen-
tial signal, required by the MAX1124 for optimum
dynamic performance. In general, the MAX1124 pro-
vides the best SFDR and THD with fully differential input
signals and it is not recommended to drive the ADC
inputs in single-ended configuration. In differential input
mode, even-order harmonics are usually lower since
INP and INN are balanced, and each of the ADC inputs
only requires half the signal swing compared to a sin-
gle-ended configuration.
Figure 8 depicts a secondary-side termination of the 1:1
transformer into two separate 25Ω loads. Terminating
the transformer in this fashion reduces the potential
effects of transformer parasitics. The source impedance
combined with the shunt capacitance provided by a
PCB and the ADC’s parasitic capacitance reduce the
combined bandwidth to approximately 550MHz.
Figure 8. Transformer-Coupled Analog Input Configuration with Secondary-Side Termination
14
Differential, AC-Coupled, PECL-Compatible
______________________________________________________________________________________
Differential, AC-Coupled Analog Input
INPUT TERMINAL
SINGLE-ENDED
0.1μF
ADT1–1WT
Clock Input
25Ω
25Ω
0.1μF
15Ω
15Ω
Although not recommended, the MAX1124 can be used
in single-ended mode (Figure 9). Analog signals can be
AC-coupled to the positive input INP through a 0.1µF
capacitor and terminated with a 50Ω resistor to AGND.
The negative input should be 25Ω reverse-terminated
and AC grounded with a 0.1µF capacitor.
The MAX1124 requires board layout design techniques
suitable for high-speed data converters. This ADC pro-
vides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switch-
ing currents, which can couple into the analog supply
network. Isolate analog and digital supplies (AV
OV
Figure 9. Single-Ended AC-Coupled Analog Input
Configuration
INN
INP
Grounding, Bypassing, and Board
CC
INPUT TERMINAL
SINGLE-ENDED
Single-Ended, AC-Coupled Analog Input
) where they enter the PCB with separate networks
MAX1124
50Ω
AV
AGND
CC
0.1μF
0.1μF
25Ω
Layout Considerations
OV
INP
INN
OGND
CC
D0P/N–D9P/N
10
MAX1124
AV
AGND
CC
OV
OGND
CC
D0P/N–D9P/N
10
CC
and