W7100A WIZnet, W7100A Datasheet - Page 8

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

Figure 5.10 Timer/Counter1, Mode0: 13-Bit Timer/Counter ........................................ 55
Figure 5.11 Timer/Counter1, Mode1: 16-Bit Timers/Counters ...................................... 55
Figure 5.12 Timer/Counter1, Mode2: 8-Bit Timer/Counter with Auto-Reload .................... 56
Figure 5.13 Timer2 Configuration Register ............................................................. 57
Figure 5.14 Timer/Counter2, 16-Bit Timer/Counter with Auto-Reload ............................ 58
Figure 5.15 Interrupt Enable Register — Timer2 ....................................................... 58
Figure 5.16 Interrupt Priority Register — Timer2 ...................................................... 59
Figure 5.17 Timer2 Configuration Register — TF2 ..................................................... 59
Figure 5.18 Timer/Counter2, 16-Bit Timer/Counter with Capture Mode .......................... 59
Figure 5.19 Timer2 for Baud Rate Generator Mode ................................................... 60
Figure 6.1 UART Buffer Register .......................................................................... 61
Figure 6.2 UART Configuration Register ................................................................. 61
Figure 6.3 UART Bits in Power Configuration Register ................................................ 62
Figure 6.4 UART Bits in Interrupt Enable Register ..................................................... 63
Figure 6.5 UART Bits in Interrupt Priority Register .................................................... 63
Figure 6.6 UART Configuration Register ................................................................. 63
Figure 6.7 Timing Diagram for UART Transmission Mode0 (clk = 88.4736 MHz) ................... 64
Figure 6.8 Timing Diagram for UART Transmission Mode1 ............................................ 64
Figure 6.9 Timing Diagram for UART Transmission Mode2 ............................................ 64
Figure 6.10 Timing Diagram for UART Transmission Mode3 .......................................... 65
Figure 7.1 Watchdog Timer Structure ................................................................... 66
Figure 7.2 Interrupt Enable Register .................................................................... 66
Figure 7.3 Extended Interrupt Enable Register ........................................................ 66
Figure 7.4 Extended interrupt Priority Register ....................................................... 67
Figure 7.5 Watchdog Control Register ................................................................... 67
Figure 7.6 Watchdog Control Register ................................................................... 69
Figure 7.7 Clock Control register – Watchdog bits..................................................... 70
Figure 8.1 TCPIPCore Memory Map ...................................................................... 71
Figure 8.2 SOCKET n Status transition................................................................... 98
Figure 8.3 Calculate Physical Address ................................................................. 105
Figure 9.1 Allocation Internal TX/RX memory of SOCKET n ........................................ 112
Figure 9.2 TCP SERVER & TCP CLIENT ................................................................. 113
Figure 9.3 “TCP SERVER” Operation Flow ............................................................ 114
Figure 9.4 “TCP CLIENT” Operation Flow ............................................................. 121
Figure 9.5 UDP Operation Flow ......................................................................... 122
Figure 9.6 The received UDP data format ............................................................ 124
Figure 9.7 IPRAW Operation Flow ...................................................................... 131
Figure 9.8 The received IPRAW data format ......................................................... 132
8
© Copyright 2011 WIZnet Co., Inc. All rights reserved.
Ver. 1.12