SiM3U157-B-GQ Silicon Labs, SiM3U157-B-GQ Datasheet - Page 3

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SiM3U157-B-GQ

Manufacturer Part Number
SiM3U157-B-GQ
Description
ARM Microcontrollers - MCU ARM Cortex-M3 USB 128KB TQFP80
Manufacturer
Silicon Labs
Datasheet

Specifications of SiM3U157-B-GQ

Rohs
yes
Core
ARM Cortex M3
Processor Series
SIM3U1xx
Data Bus Width
32 bit
Maximum Clock Frequency
80 MHz
Program Memory Size
128 KB
Data Ram Size
32 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TQFP-80
Mounting Style
SMD/SMT
Interface Type
2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
65
Number Of Timers
2 x 32 bit
Supply Voltage - Max
3.6 V
Supply Voltage - Min
1.8 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SIM3U157-B-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SiM3U157-B-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
5. Ordering Information .........................................................................................................52
6. Pin Definitions and Packaging Information.....................................................................54
7. Revision Specific Behavior............................................................................................... 90
Document Change List ........................................................................................................... 92
Contact Information ................................................................................................................ 94
4.7. Analog .......................................................................................................................... 48
4.8. Reset Sources..............................................................................................................50
4.9. Security ........................................................................................................................ 51
4.10.On-Chip Debugging ..................................................................................................... 51
6.1. SiM3U1x7 Pin Definitions............................................................................................. 54
6.2. SiM3U1x6 Pin Definitions............................................................................................. 62
6.3. SiM3U1x4 Pin Definitions............................................................................................. 69
6.4. LGA-92 Package Specifications...................................................................................73
6.5. TQFP-80 Package Specifications ................................................................................ 76
6.6. QFN-64 Package Specifications .................................................................................. 80
6.7. TQFP-64 Package Specifications ................................................................................ 83
6.8. QFN-40 Package Specifications .................................................................................. 87
7.1. Revision Identification .................................................................................................. 90
7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1)...................... 91
4.6.5. SPI (SPI0, SPI1) .................................................................................................. 46
4.6.6. I2C (I2C0, I2C1)................................................................................................... 46
4.6.7. I2S (I2S0)............................................................................................................. 47
4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1).............................. 48
4.7.2. Sample Sync Generator (SSG0) ......................................................................... 48
4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ............................................ 48
4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) ............................ 49
4.7.5. Low Current Comparators (CMP0, CMP1) .......................................................... 49
4.7.6. Current-to-Voltage Converter (IVC0) ................................................................... 49
6.4.1. LGA-92 Solder Mask Design ............................................................................... 75
6.4.2. LGA-92 Stencil Design ........................................................................................ 75
6.4.3. LGA-92 Card Assembly ....................................................................................... 75
6.5.1. TQFP-80 Solder Mask Design............................................................................. 79
6.5.2. TQFP-80 Stencil Design ...................................................................................... 79
6.5.3. TQFP-80 Card Assembly..................................................................................... 79
6.6.1. QFN-64 Solder Mask Design............................................................................... 82
6.6.2. QFN-64 Stencil Design ........................................................................................ 82
6.6.3. QFN-64 Card Assembly....................................................................................... 82
6.7.1. TQFP-64 Solder Mask Design............................................................................. 86
6.7.2. TQFP-64 Stencil Design ...................................................................................... 86
6.7.3. TQFP-64 Card Assembly..................................................................................... 86
6.8.1. QFN-40 Solder Mask Design............................................................................... 89
6.8.2. QFN-40 Stencil Design ........................................................................................ 89
6.8.3. QFN-40 Card Assembly....................................................................................... 89
7.2.1. Problem ...............................................................................................................91
7.2.2. Impacts ................................................................................................................ 91
7.2.3. Workaround ......................................................................................................... 91
7.2.4. Resolution............................................................................................................ 91
Rev. 1.0
SiM3U1xx
3

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