MAX1036KEKA-T Maxim Integrated, MAX1036KEKA-T Datasheet - Page 5

• Manufacturer Part Number: MAX1036KEKA-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1036KEKA-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 188 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 49 dB
• Interface Type: Serial (2-Wire, I2C)
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Package / Case: SOT-23
• Maximum Power Dissipation: 567 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

ELECTRICAL CHARACTERISTICS (continued)
(V
(MAX1037/MAX1039), V
noted. Typical values are at T
Note 1: The MAX1036/MAX1038 are tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V
Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV
Note 10: Electrical characteristics are guaranteed from V
Note 11: Power-supply rejection ratio is measured as:
Note 12: A master device must provide a data hold time for SDA (referred to V
Note 13: C
Note 14: f
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
DD
= 2.7V to 3.6V (MAX1037/MAX1039), V
Power-supply rejection ratio is measured as:
ured for unipolar, single-ended inputs.
offsets have been calibrated.
include acquisition time. SCL is the conversion clock in the external clock mode.
Operating Characteristics .
specified at +25°C with C
SCL’s falling edge (Figure 1).
[
[
SCLH
PARAMETER
V
V
B
FS
FS
= total capacitance of one bus line in pF. t
(
(
3 3
5 5
must meet the minimum clock low time plus the rise/fall times.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
.
.
V
V
)
3 3
)
5 5
−
_______________________________________________________________________________________
.
−
.
V
V
V
V
FS
FS
REF
−
−
(
(
2 7
4 5
2 7
4-/12-Channel 2-Wire Serial 8-Bit ADCs
4 5
.
.
.
.
= 4.096V (MAX1036/MAX1038). External clock, f
A
V
V
V
V
= +25°C.)
)
)
]
]
×
×
V
B
V
2
REF
2
REF
= 400pF.
SYMBOL
N
N
t
t
t
t
HD
SU
SU
SU
t
t
t
t
RCL1
t
RCL
RDA
FDA
FCL
C
t
,
,
,
,
SP
, for the MAX1037/MAX1039 where N is the number of bits and V
, for the MAX1036/MAX1038 where N is the number of bits and V
B
DAT
STO
STA
DAT
(Note 12)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
DD
DD
= 5V and the MAX1037/MAX1039 are tested at V
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
R
, t
DD(min)
FDA
, and t
CONDITIONS
to V
F
DD(max)
measured between 0.3V
. For operation beyond this range, see the Typical
SCL
IL
of SCL) in order to bridge the undefined region of
P-P
= 1.7MHz, T
.
DD
.
DD
A
= T
MIN
and 0.7V
160
160
10
20
20
20
20
20
0
0
DD
MIN
= 3V. All devices are config-
REF
to T
REF
DD
TYP
. The minimum value is
MAX
= 2.048V.
= 4.096V.
, unless otherwise
MAX
150
160
160
160
400
80
80
10
REF
= 2.048V
UNITS
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5