LTC1555IGN Linear Technology, LTC1555IGN Datasheet - Page 8

• Manufacturer Part Number: LTC1555IGN
• Description: IC LEVEL TRANSLATOR 16-SSOP
• Manufacturer: Linear Technology

Specifications of LTC1555IGN

• Logic Function: Level Shifter
• Number Of Bits: 1
• Input Type: Voltage
• Output Type: Voltage
• Number Of Channels: 1
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 18ns
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SSOP
• Supply Voltage: 1.8 V ~ 5.5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -

APPLICATIONS
LTC1555/LTC1556
reduce the ripple. A larger C
will reduce both the low and high frequency ripple due to
the lower C
lower ESR typically found with higher value (larger case
size) capacitors. A low ESR ceramic output capacitor will
minimize the high frequency ripple, but will not reduce the
low frequency ripple unless a high capacitance value is
chosen (10 F or greater). A reasonable compromise is to
use a 10 F to 22 F tantalum capacitor in parallel with a 1 F
to 3.3 F ceramic capacitor on V
and high frequency ripple. An RC filter may also be used
to reduce high frequency voltage spikes (see Figure 1).
Shutting Down the DV
To conserve power, the DV
while the V
is brought to 0V, weak internal currents will force the
LTC1555/LTC1556 into shutdown mode regardless of the
voltages present on the M0 and M1 pins. However, if the
M0 and M1 pins are floating or left connected to DV
the supply is shut down, the parts may take several
8
M0
M1
DV
V
Figure 2. Recommended DV
CC
CC
DV
DV
DV
Figure 1. V
V
0V
0V
0V
0V
CC
CC
CC
CC
IN
LTC1555/
LTC1556
OUT
supply is still active. When the DV
V
V
CC
CC
charging and discharging dV/dt and the
CC
Output Ripple Reduction Techniques
U
+
CC
15 F
TANTALUM
10 F
INFORMATION
Supply
U
CC
OUT
CC
2
Shutdown and Start-Up Timing
capacitor (22 F or greater)
supply may be shut down
OUT
to reduce both the low
W
1 F
CERAMIC
10 F
LT1555/56 F01
SIM
V
SIM
V
CC
CC
U
CC
supply
1555/56 F02
CC
as
hundred milliseconds to completely shut down. To ensure
prompt and proper V
and M1 pins to a logic low state before shutting down the
DV
supply to a valid level before allowing the M0 and M1 pins
to go high when coming out of shutdown. This can be
achieved with pull-down resistors from M0 and M1 to
GND if necessary. (Note: shutting down the DV
with V
material. Consult factory for valid date code starting point
for shutting down the DV
Level Translators
All SIMs and smart cards contain a clock input, reset input
and a bidirectional data input/output. The LTC1555/
LTC1556 provide level translators to allow controllers to
communicate with the SIM (see Figures 3a and 3b). The
CLK and RST inputs to the SIM are level shifted from the
controller supply rails (DV
rails (V
provided two different ways. The first method is to use the
DATA pin as a bidirectional level translator. This configu-
ration is only allowed if the controller data output pin is
open drain (all SIM I/O pins are open drain). Internal pull-
up resistors are provided for both the DATA pin and the
DATA TO/FROM SIM
CC
DATA FROM SIM
CONTROLLER
CONTROLLER
supply (see Figure 2). Similarly, bring the DV
IN
DATA TO SIM
CC
RST TO SIM
RST TO SIM
CLK TO SIM
CLK TO SIM
SIDE
SIDE
active is not recommended with early date code
Figure 3a. Level Translator Connections for
Bidirectional Controller DATA Pin
Figure 3b. Level Translator Connections for
One-Directional Controller Side DATA Flow
and GND). The data input to the SIM may be
CC
LTC1555/LTC1556
LTC1555/LTC1556
CIN
RIN
DATA
DDRV
DV
CIN
RIN
DATA
DDRV
DV
shutdown, always force the M0
CC
CC
CC
CC
supply.)
and GND) to the SIM supply
CLK
RST
CLK
RST
V
V
I/O
I/O
CC
CC
SIM SIDE
SIM SIDE
1555/56 F3a
1555/56 F3b
CC
supply
CC