EFM32WG840F128 Energy Micro, EFM32WG840F128 Datasheet - Page 7

• Manufacturer Part Number: EFM32WG840F128
• Description: ARM Microcontrollers - MCU 128kb flash 32kb RAM
• Manufacturer: Energy Micro

Specifications of EFM32WG840F128

• Rohs: yes
• Core: ARM Cortex M4F
• Processor Series: EFM32WG840
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 48 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.85 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-64
• Mounting Style: SMD/SMT

2.1.27 General Purpose Input/Output (GPIO)
2.1.28 Liquid Crystal Display Driver (LCD)
2.2 Configuration Summary
2012-09-11 - EFM32WG840FXX - d0195_Rev1.00
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
In the EFM32WG840, there are 56 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advances configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
The LCD driver is capable of driving a segmented LCD display with up to segments. A voltage boost
function enables it to provide the LCD display with higher voltage than the supply voltage for the device.
In addition, an animation feature can run custom animations on the LCD display without any CPU inter-
vention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter
interrupt that can wake-up the device on a regular basis for updating data.
The features of the EFM32WG840 is a subset of the feature set described in the EFM32WG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M4F
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
I2C0
I2C1
USART0
USART1
USART2
LEUART0
LEUART1
Preliminary
Configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
IrDA
I2S
I2S
Full configuration
Full configuration
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7
Pin Connections
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
I2C0_SDA, I2C0_SCL
I2C1_SDA, I2C1_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
US2_TX, US2_RX, US2_CLK, US2_CS
LEU0_TX, LEU0_RX
LEU1_TX, LEU1_RX
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