74LVC543ABQ-G NXP Semiconductors, 74LVC543ABQ-G Datasheet - Page 4

• Manufacturer Part Number: 74LVC543ABQ-G
• Description: Bus Transceivers OCTAL REG XCVR 3-S
• Manufacturer: NXP Semiconductors

Specifications of 74LVC543ABQ-G

• Product Category: Bus Transceivers
• Rohs: yes
• Logic Type: CMOS
• Logic Family: LVC
• Number Of Channels Per Chip: 8
• Input Level: LVTTL
• Output Level: LVTTL
• Output Type: 3-State
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 15 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.2 V
• Maximum Operating Temperature: + 125 C
• Package / Case: DHVQFN-24
• Function: Latched Transceiver
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Circuits: 1
• Polarity: Non-Inverting
• Factory Pack Quantity: 3000
• Part # Aliases: 74LVC543ABQ,115

NXP Semiconductors
5. Pinning information
Table 2.
74LVC543A_8
Product data sheet
Symbol
LEBA
LEAB
OEBA
OEAB
EBA
EAB
A[0:7]
B[0:7]
GND
V
Fig 4.
CC
Pin configuration for SO24 and (T)SSOP24
Pin description
OEBA
LEBA
GND
EAB
A0
A1
A2
A3
A4
A5
A6
A7
5.1 Pinning
5.2 Pin description
Pin
1
14
2
13
23
11
3, 4, 5, 6, 7, 8, 9, 10
22, 21, 20, 19, 18, 17, 16, 15
12
24
10
12
11
1
2
3
4
5
6
7
8
9
74LVC543A
001aaa341
24
23
22
21
20
19
18
17
16
15
14
13
All information provided in this document is subject to legal disclaimers.
V
EBA
B0
B1
B2
B3
B4
B5
B6
B7
LEAB
OEAB
CC
Rev. 8 — 18 December 2012
Description
B to A latch enable input (active LOW)
A to B latch enable input (active LOW)
B to A output enable input (active LOW)
A to B output enable input (active LOW)
B to A enable input (active LOW)
A to B enable input (active LOW)
A data input or output
B data output or input
ground (0 V)
supply voltage
Fig 5.
(1) This is not a supply pin. The substrate is attached to this
index area
terminal 1
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Pin configuration for DHVQFN24
Octal D-type registered transceiver; 3-state
OEBA
EAB
A0
A1
A2
A3
A4
A5
A6
A7
10
11
2
3
4
5
6
7
8
9
Transparent top view
GND
74LVC543A
(1)
74LVC543A
© NXP B.V. 2012. All rights reserved.
23
22
21
20
19
18
17
16
15
14
001aaa340
EBA
B0
B1
B2
B3
B4
B5
B6
B7
LEAB
4 of 20