MAX5702AAUB+T Maxim Integrated, MAX5702AAUB+T Datasheet - Page 16

• Manufacturer Part Number: MAX5702AAUB+T
• Description: Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/SPI
• Manufacturer: Maxim Integrated

Specifications of MAX5702AAUB+T

• Rohs: yes

The MAX5700/MAX5701/MAX5702 3-wire serial interface
is compatible with MICROWIRE, SPI, QSPI, and DSPs.
The interface provides three inputs, SCLK, CSB, and
DIN. The chip-select input (CSB, active low) frames the
data loaded through the serial data input (DIN). Following
a CSB input high-to-low transition, the data is shifted
in synchronously and latched into the input register on
each falling edge of the serial clock input (SCLK). Each
serial operation word is 24-bits long. The DAC data is
left justified as shown in Table 1. The serial input register
transfers its contents to the destination registers after
loading 24 bits of data on the 24th SCLK falling edge.
To initiate a new SPI operation, drive CSB high and then
low to begin the next operation sequence, being sure to
meet all relevant timing requirements. During CSB high
periods, SCLK is ignored, allowing communication to
other devices on the same bus. SPI operations consist-
ing of more than 24 SCLK cycles are executed on the
24th SCLK falling edge, using the first three bytes of
data available. SPI operations consisting of less than 24
SCLK cycles will not be executed. The content of the SPI
operation consists of a command byte followed by a two
byte data word.
Figure 1 shows the timing diagram for the complete
3-wire serial interface transmission. The DAC code
settings (D) for the MAX5700/MAX5701/MAX5702 are
accepted in an offset binary format (see
Otherwise, the expected data format for each command
is listed in
cal SPI circuit application.
Maxim Integrated
Table 1. Format DAC Data Bit Positions
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
MAX5700
MAX5701
MAX5702
PART
Table
B15
D11
D7
D9
DACs with Internal Reference and SPI Interface
2. See Figure 2 for an example of a typi-
B14
D10
D6
D8
B13
D5
D7
D9
SPI Serial Interface
B12
D4
D6
D8
B11
D7
D3
D5
Table
B10
D2
D4
D6
MAX5700/MAX5701/MAX5702
1).
B9
D1
D3
D5
D2
D4
B8
D0
Figure 2. Typical SPI Application Circuit
This section lists the user accessible commands and
registers for the MAX5700/MAX5701/MAX5702.
Table 2
Registers.
*ADDITIONAL SPI DEVICE
B7
D1
D3
x
provides detailed information about the Command
µC
B6
D0
D2
x
SPI User-Command Register Map
CSB1
SCLK
MOSI
CSB2
MISO
CSB3
D1
B5
x
x
B4
D0
x
x
B3
x
x
x
CSB
SCLK
DIN
CSB
SCLK
DIN
DOUT
CSB
SCLK
DIN
B2
x
x
x
MAX5700
MAX5701
MAX5702
B1
x
x
x
*
*
B0
x
x
x
16