MAX5259EEE-T Maxim Integrated, MAX5259EEE-T Datasheet - Page 6

• Manufacturer Part Number: MAX5259EEE-T
• Description: Digital to Analog Converters - DAC 8-Bit 8Ch Precision DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5259EEE-T

• Number Of Converters: 8
• Number Of Dac Outputs: 8
• Resolution: 8 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, 4-Wire, Microwire)
• Settling Time: 7 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
TIMING CHARACTERISTICS (MAX5259)
(V
T
Note 1: INL and DNL are measured with R
Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of V
Note 3: Guaranteed by design, not production tested.
Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for t
Note 5: When DOUT is not used. If DOUT is used, f
Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V
6
A
V
LDAC Pulse Width Low
CS Rise-to-LDAC Fall-Setup Time
(Note 4)
CS Pulse Width High
SCLK Clock Frequency (Note 5)
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall-to-SCLK Rise-Setup Time
SCLK Rise-to-CS Rise-Hold Time
DIN to SCLK Rise-to-Setup Time
DIN to SCLK Rise-to-Hold Time
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
CS Rise-to-SCLK Rise-Setup
Time
REF
DD
= +25°C.)
_______________________________________________________________________________________
Rise-to-CS Fall-Setup Time
= +2.5V, GND = 0, C
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
PARAMETER
DOUT
= 100pF, T
SYMBOL
t
t
t
VDCS
LDAC
f
t
t
t
t
t
t
CSW
CLK
t
CSS
CSH
t
t
DO1
DO2
CLL
t
CS1
CH
DS
DH
CL
L
referenced to ground. Nonlinearity is measured from the first code that is greater than or
A
= T
CLK
MIN
(max) is 4MHz due to SCLK to DOUT propagation delay.
to T
MAX
CONDITIONS
, unless otherwise noted. Typical values are at V
LDAC
or longer after CS goes high.
MIN
40
40
90
40
40
40
40
40
0
0
TYP
20
10
5
DD
DD
OUT
MAX
200
210
DD
).
).
.
= +3V and
UNITS
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns