MAX548AEPA Maxim Integrated, MAX548AEPA Datasheet - Page 9

• Manufacturer Part Number: MAX548AEPA
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX548AEPA

• Number Of Converters: 2
• Number Of Dac Outputs: 2
• Resolution: 8 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, 4-Wire, Microwire)
• Settling Time: 4 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP N
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.5 V
• Voltage Reference: External

Table 2. MAX548A Serial-Interface Programming Commands
UB1
UNASSIGNED COMMANDS
COMMANDS LOADING INPUT REGISTER(S) ONLY
COMMANDS UPDATING DAC REGISTER(S)
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
UB2
8-Bit Voltage-Output DACs in µMAX Package
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
UB3
CONTROL BYTE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Loaded First
_______________________________________________________________________________________
+2.5V to +5.5V, Low-Power, Single/Dual,
C2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C1
0
X
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
C0
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
1
1
A1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Loaded Last
DATA BYTE
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
D7........D0
LDAC
Pin 6
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
Unassigned command
Unassigned operation
Load DAC A input register. DAC B input register
and both DAC registers unchanged.
Load DAC B input register. DAC A input register
and both DAC registers unchanged.
Load both DAC input registers. Both DAC regis-
ters unchanged.
Update both DAC registers with current contents
of their input registers. Both input registers
unchanged.
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
Load both DAC input registers and update both
DAC registers.
Update both DAC registers with current contents
of their input registers. Both input registers
unchanged.
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
Load both DAC input registers and update both
DAC registers.
After CS’s rising edge and on LDAC’s falling
edge, update both DAC registers with current
contents of their input registers. Both input regis-
ters unchanged.
Load DAC A input register. After CS’s rising edge
and on LDAC’s falling edge, update both DAC
registers.
Load DAC B input register. After CS’s rising edge
and on LDAC’s falling edge, update both DAC
registers.
Load both DAC input registers. After CS’s rising
edge and on LDAC’s falling edge, update both
DAC registers.
(Commands executed on
COMMAND
CS’s rising edge)
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