MAX532BC/D Maxim Integrated, MAX532BC/D Datasheet - Page 3

• Manufacturer Part Number: MAX532BC/D
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX532BC/D

• Number Of Converters: 2
• Number Of Dac Outputs: 2
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: Die
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: 0 C
• Output Type: Voltage Buffered
• Supply Current: 5 mA
• Supply Voltage - Max: 16.5 V
• Supply Voltage - Min: 11.4 V
• Voltage Reference: External

Positive Supply Current
Negative Supply Current
TIMING
CHARACTERISTICS
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Rise Setup
Time
DIN to SCLK Rise Hold
Time
__
CS Fall to SCLK Rise
Setup Time
__
CS Rise to SCLK Rise
Setup Time
SCLK Fall to CS Fall
Hold Time
SCLK Rise to CS Rise
Hold Time
__
CS Pulse Width High
SCLK Fall to DOUT
Valid
__
CS Fall to DOUT Enable
__
CS Rise to DOUT Disable
_____
LDAC Pulse Width Low
__
CS Rise to LDAC Fall
Setup Time
TEST
_____
NOTE 1: V
NOTE 2: Static performance tested at V
NOTE 3: Guaranteed by design. Not subject to production testing.
NOTE 4: Open-drain output.
NOTE 5: All input signals are specified with t
NOTE 6: See Figure 1 in commercial datasheet.
NOTE 7: Timing is for SCLK fall to DOUT fall to 0.8V or for SCLK fall to DOUT rise to 2.4V. Additional time
NOTE 8: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
----------------------------
__
__
VREFB=+10V, R
must be added for any larger passive RC pull-up delay.
DD
=11.4V to 16.5V, V
Symbol
I
I
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
SS
CLK
CH
CL
DS
DH
CSSO
CSS1
CSHO
CSH1
CSW
DO
DV
TR
LDAC
LDACS
Electrical Characteristics of MAX532/883B for
/883B and SMD 5962-95667
L
=2k , C
-55 C T
Unless otherwise specified
Output unloaded
Output unloaded
NOTES 5, 6
CL=20pF, Rpull-up=1k to 5V
NOTE 7
CL=20pF, Rpull-up=1k to 5V
NOTE 8
CL=20pF, Rpull-up=1k to 5V
NOTE 8
SS
CONDITIONS
=-11.4 to -16.5V, AGNDA=AGNDB=DGND=0V, VREFA and
L
=100pF, V
A
DD
=+15V, V
+125 C 1/
R
=t
F
OUT
5ns. Logic input swing is 0V to 5V.
_ connected to RFB_.
SS
=-15V. Performance over supplies guaranteed by PSR test.
Group A
Subgroup
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
1,2,3
1,2,3
Device
type
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
All
19-0408
Page 4 of
Limits
Min
120
100
80
80
50
50
50
80
60
0
5
0
Limits
Rev. B
7
Max
6.25
200
100
10
60
6
Units
mA
mA
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns