MAX5581EVCMODU Maxim Integrated, MAX5581EVCMODU Datasheet - Page 28

• Manufacturer Part Number: MAX5581EVCMODU
• Description: Digital to Analog Converters - DAC MAXIM EVALUATION SYSTEM
• Manufacturer: Maxim Integrated

Specifications of MAX5581EVCMODU

• Number Of Converters: 4
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V

Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
Table 21 lists the possible configurations for UPIO1 and
UPIO2. UPIO1 and UPIO2 use the selected function
when configured by the UP3–UP0 configuration bits.
LDAC controls the loading of the DAC registers. When
LDAC is high, the DAC registers are latched, and any
change in the input registers does not affect the con-
tents of the DAC registers or the DAC outputs. When
LDAC is low, the DAC registers are transparent, and the
values stored in the input registers are fed directly to the
DAC registers, and the DAC outputs are updated.
Table 21. UPIO Configuration Register Bits (UP3–UP0)
28
UP3
UPIO CONFIGURATION BITS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
______________________________________________________________________________________
UP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
UP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
UP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UPIO Configuration
FUNCTION
SHDN100K
DOUTDC0
DOUTDC1
Reserved
SHDN1K
DOUTRB
GPOH
TOGG
GPOL
LDAC
FAST
CLR
PDL
SET
MID
GPI
Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers
with data from input registers.
Active-Low Input. Drive low to set all input and DAC registers to full scale.
Active-Low Input. Drive low to set all input and DAC registers to midscale.
Active-Low Input. Drive low to set all input and DAC registers to zero scale.
Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.
This mode is reserved. Do not use.
Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5580/MAX5582/MAX5584, drive SHDN1K low to pull OUTA–OUTD to AGND
with 1kΩ. For the MAX5581/MAX5583/MAX5585, drive SHDN1K low to leave
OUTA–OUTD high impedance.
Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5580/MAX5582/MAX5584, drive SHDN100K low to pull OUTA–OUTD to
AGND with 100kΩ. For the MAX5581/MAX5583/MAX5585, drive low to leave
OUTA–OUTD high impedance.
Data Read-Back Output
M od e 0 D ai sy- C hai n D ata O utp ut. D ata i s cl ocked out on the fal l i ng ed g e of S C LK.
Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.
General-Purpose Logic Input
General-Purpose Logic-Low Output
General-Purpose Logic-High Output
Toggle Input. Toggles DAC outputs between data in input registers and data in
DAC registers. Drive low to set all DAC outputs to values stored in input registers.
Drive high to set all DAC outputs to values stored in DAC registers.
Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive
high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDD settings.
LDAC
Drive LDAC low to asynchronously load the DAC regis-
ters from their corresponding input registers (DACs that
are in shutdown remain shut down). The LDAC input
does not require any activity on CS, SCLK, or DIN to
take effect. If LDAC is brought low coincident with a ris-
ing edge of CS (which executes a serial command
modifying the value of either DAC input register), then
LDAC must remain asserted for at least 120ns following
the CS rising edge. This requirement applies only for
serial commands that modify the value of the DAC input
registers. See Figures 5 and 6 for timing details.
DESCRIPTION