MAX536AEPE Maxim Integrated, MAX536AEPE Datasheet - Page 22

• Manufacturer Part Number: MAX536AEPE
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX536AEPE

• Number Of Converters: 4
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, 4-Wire, Microwire)
• Settling Time: 3 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP N
• Maximum Power Dissipation: 842 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Current: 8 mA
• Supply Voltage - Max: - 5.5 V, + 16.5 V
• Supply Voltage - Min: - 4.5 V, + 10.8 V
• Voltage Reference: External

In applications where the reference has AC signal compo-
nents, the MAX536/MAX537 have multiplying capability
within the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to the
reference input where the AC signal is offset before being
applied to REFAB/REFCD. The reference voltage must
never be more negative than DGND.
The MAX536’s total harmonic distortion plus noise
(THD+N) is typically less than 0.012%, given a 5V
swing and input frequencies up to 35kHz, or given a 2V
swing and input frequencies up to 50kHz. The typical -3dB
frequency is 700kHz as shown in the Typical Operating
Characteristics graphs.
For the MAX537, with an input signal amplitude of
0.85mV
5kΩ load in parallel with 100pF and input frequencies up
to 100kHz, or with a 2kΩ load in parallel with 100pF and
input frequencies up to 95kHz.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Figure 14. When V
Schottky diode between V
22
______________________________________________________________________________________
P-P
1N5817
, THD+N is typically less than 0.024% with a
SS
and V
SS
3
4
DD
V
AGND
and AGND.
Using an AC Reference
SS
cannot be sequenced, tie a
MAX536
MAX537
P-P
signal
P-P
AGND can be biased from DGND to the reference voltage
to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage V
where V
to DGND) applied to AGND, and N
value of the DAC’s binary input code. Since AGND is
common to all four DACs, all outputs will be offset by
V
increases, the DAC’s resolution decreases because its
full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
On power-up, V
REFAB or REFCD. If supply sequencing is not possible,
tie an external Schottky diode between V
as shown in Figure 14. On power-up, all input and DAC
registers are cleared (set to zero code) and SDO is in
Mode 0 (serial data is shifted out of SDO on the clock’s
rising edge).
For rated MAX536 performance, V
higher than REFAB/REFCD and should be between
10.8V and 13.2V. When using the MAX537, V
be at least 2.2V higher than REFAB/REFCD and should
be between 4.75V and 5.5V. Bypass both V
with a 4.7µF capacitor in parallel with a 0.1µF capacitor
to AGND. Use short lead lengths and place the bypass
capacitors as close to the supply pins as possible.
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest quality ground available.
Good PCB ground layout minimizes crosstalk between
DAC outputs, reference inputs, and digital inputs.
Reduce crosstalk by keeping analog lines away from
digital lines. Wire-wrapped boards are not recommend-
ed.
BIAS
in the same manner. As the voltage at AGND
Grounding and Layout Considerations
BIAS
is the positive offset voltage (with respect
V
SS
OUTA
Power-Supply Considerations
should come up first, V
= V
BIAS
+ N
B
Offsetting AGND
(V
DD
B
IN
)
is the numeric
should be 4V
SS
DD
DD
OUTA
and AGND
DD
next, then
and V
should
is:
SS