M24256-DRMN6TP STMicroelectronics, M24256-DRMN6TP Datasheet - Page 16

• Manufacturer Part Number: M24256-DRMN6TP
• Description: EEPROM 256 Kbit serial I2C EEPROM 3 Chip
• Manufacturer: STMicroelectronics

Specifications of M24256-DRMN6TP

• Product Category: EEPROM
• Rohs: yes

Instructions
5.1.2
16/40
Page Write
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8.
WC
Byte Write
WC
Page Write
WC (cont'd)
Page Write (cont'd)
Figure
Write mode sequences with WC = 1 (data write inhibited)
8. After each transferred byte, the internal page address counter is
NO ACK
Dev sel
Dev sel
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Data in N
Doc ID 6757 Rev 30
R/W
R/W
ACK
ACK
NO ACK
Byte addr
Byte addr
ACK
ACK
Byte addr
Byte addr
ACK
ACK
Data in 1
Data in
NO ACK
NO ACK
Data in 2
AI01120d