CAV24C08YE-GT3 ON Semiconductor, CAV24C08YE-GT3 Datasheet

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CAV24C08YE-GT3

Manufacturer Part Number
CAV24C08YE-GT3
Description
EEPROM 8KB I2C SER EEPROM
Manufacturer
ON Semiconductor
Datasheet

Specifications of CAV24C08YE-GT3

Product Category
EEPROM
Rohs
yes
Memory Size
8 Kbit
Organization
1 K x 8
Data Retention
100 Years
Maximum Clock Frequency
0.1 MHz
Maximum Operating Current
2 mA
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 125 C
Package / Case
TSSOP-8
Access Time
3500 ns
Interface Type
IC2
Minimum Operating Temperature
- 40 C
Supply Voltage - Max
5.5 V
Supply Voltage - Min
2.5 V
CAV24C02, CAV24C04,
CAV24C08, CAV24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I
Description
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I
protocol.
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16
device on the same bus.
Features
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 2
2
The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
Data is written by providing a starting address, then loading 1 to 16
External address pins make it possible to address up to eight
and Change Control
(SCL and SDA)
Compliant
Automotive Temperature Grade 1 (−40°C to +125°C)
Supports Standard and Fast I
2.5 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
CAV Prefix for Automotive and Other Applications Requiring Site
Schmitt Triggers and Noise Suppression Filters on I
Low power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
C CMOS Serial EEPROM
A
2
, A
1
SCL
, A
WP
0
Figure 1. Functional Symbol
CAV24Cxx
V
V
CC
SS
2
C Protocol
SDA
2
C Bus Inputs
1
2
C
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
NC /
NC NC
NC
16 / 08 / 04 / 02
A0, A1, A2
Pin Name
/
/
CAV24C__
SDA
SCL
V
V
WP
CASE 948AL
NC
NC NC
A
CC
SS
TSSOP−8
Y SUFFIX
2
ORDERING INFORMATION
/
/
/
PIN CONFIGURATIONS
A
A
SOIC (W), TSSOP (Y)
1
2
http://onsemi.com
PIN FUNCTION
/
/
/
V
A
A
A
SS
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
0
1
2
(Top View)
Publication Order Number:
1
2
3
4
Function
CASE 751BD
W SUFFIX
SOIC−8
8
7
6
5
CAV24C02/D
V
WP
SCL
SDA
CC

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CAV24C08YE-GT3 Summary of contents

Page 1

... I C CMOS Serial EEPROM Description The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb respectively CMOS Serial EEPROM devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I protocol. Data is written by providing a starting address, then loading contiguous bytes into a Page Write Buffer, and then writing all data to non− ...

Page 2

CSSS AYMXXX G CSSS = Specific Device Code, where SSS = 02H for CAV24C02 SSS = 04K for CAV24C04 SSS = 08K for CAV24C08 SSS = 16K for CAV24C16 A = Assembly Location Y = Production Year (Last Digit) ...

Page 3

Table 4. PIN IMPEDANCE CHARACTERISTICS Symbol Parameter C (Note 4) SDA Pin Capacitance IN Other Pins I (Note 5) WP Input Current WP I (Note 5) Address Input Current A (A0, A1, A2) Product Rev H 4. These parameters are ...

Page 4

... SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. ...

Page 5

SCL SDA START CONDITION BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START SCL t SU:STA t HD:SDA SDA IN SDA OUT ...

Page 6

Byte Write In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is ...

Page 7

SCL th SDA 8 Bit Byte n S BUS ACTIVITY SLAVE R MASTER ADDRESS SLAVE ADDRESS BYTE 1 SCL a 7 SDA WP ACK t WR STOP ...

Page 8

Immediate Read Upon receiving a Slave address with the R/W bit set to ‘1’, the CAV24Cxx will interpret this as a request for data residing at the current byte address in memory. The CAV24Cxx will acknowledge the Slave address, will ...

Page 9

PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...

Page 10

E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...

Page 11

... The device used in the above example is a CAV24C16WE−GT3 (SOIC, Automotive Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 12. For availability of other package options, please contact your nearest ON Semiconductor Sales Office. 13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

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