CAT25020HU4I-GT3 ON Semiconductor, CAT25020HU4I-GT3 Datasheet - Page 9

• Manufacturer Part Number: CAT25020HU4I-GT3
• Description: EEPROM 2KB SPI SER CMOS EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAT25020HU4I-GT3

• Rohs: yes
• Memory Size: 2 KB
• Organization: 256 x 8
• Data Retention: 100 yr
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Current: 2 mA
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UDFN-8

Read from Memory Array
followed by a 8−bit address (for the CAT25040, bit 3 of the
read instruction opcode contains A8 address bit).
will respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
SCK
SCK
To read from memory, the host sends a READ instruction
After receiving the last address bit, the CAT25010/20/40
CS
CS
SO
SO
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
0
0
0
0
0
1
0
0
2
1
0
3
HIGH IMPEDANCE
OPCODE
OPCODE
0
X*
2
4
0
0
HIGH IMPEDANCE
5
3
1
6
0
4
1
7
A
8
7
1
5
Figure 10. RDSR Timing
Figure 9. READ Timing
READ OPERATIONS
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9
BYTE ADDRESS
6
0
1
9
7
12
Read Status Register
command. After receiving the last bit of the command, the
CAT25010/20/40 will shift out the contents of the status
register on the SO pin (Figure 10). The status register may
be read at any time, including during an internal write cycle.
command will output the full content of the status register
(New product, Rev. E) or the RDY (Ready) bit only (i.e.,
data out = FFh) for previous product revisions C, D (Mature
product). For easy detection of the internal write cycle
completion, both during writing to the memory array and to
the status register, we recommend sampling the RDY bit
only through the polling routine. After detecting the RDY bit
“0”, the next RDSR instruction will always output the
expected content of the status register.
MSB
To read the status register, the host simply sends a RDSR
While the internal write cycle is in progress, the RDSR
13
8
7
14 15 16 17 18 19
9
6
A
0
10
MSB
5
D7 D6 D5 D4 D3 D2 D1 D0
11
4
DATA OUT
12
3
DATA OUT
20 21 22
13
2
14
1
0