M95M01-DFCS6TP/K STMicroelectronics, M95M01-DFCS6TP/K Datasheet - Page 18
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M95M01-DFCS6TP/K
Manufacturer Part Number
M95M01-DFCS6TP/K
Description
EEPROM 1Mb serial SPI bus 16MHz 1.7V to 5.5V
Manufacturer
STMicroelectronics
Datasheet
1.M95M01-DFCS6TPK.pdf
(45 pages)
Specifications of M95M01-DFCS6TP/K
Rohs
yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M95M01-DFCS6TP/K
Manufacturer:
ST
Quantity:
20 000
Instructions
6.2
18/45
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Figure 9.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
9, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 13264 Rev 11
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI03750D
M95M01-DF M95M01-R