M95256-DFCS6TP/K STMicroelectronics, M95256-DFCS6TP/K Datasheet - Page 18
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M95256-DFCS6TP/K
Manufacturer Part Number
M95256-DFCS6TP/K
Description
EEPROM 256Kb serial SPI bus 20 MHz 5ms 64 Byte
Manufacturer
STMicroelectronics
Datasheet
1.M95256-DFCS6TPK.pdf
(53 pages)
Specifications of M95256-DFCS6TP/K
Rohs
yes
Available stocks
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Part Number
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Instructions
6.2
18/53
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Figure 9.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
9, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 12276 Rev 19
High Impedance
0
1
2
Instruction
M95256-W M95256-R M95256-DR M95256-DF
3
4
5
6
7
AI03750D