M24256-DFDW6TP STMicroelectronics, M24256-DFDW6TP Datasheet - Page 12

• Manufacturer Part Number: M24256-DFDW6TP
• Description: EEPROM 256-Kbit I2C EEProm 32kB 1MHz 1.7 5.5V
• Manufacturer: STMicroelectronics

Specifications of M24256-DFDW6TP

• Rohs: yes

Device operation
4.1
4.2
4.3
4.4
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Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
th
clock pulse period, the receiver pulls Serial Data (SDA) low to
M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF
Doc ID 6757 Rev 30