M95320-DRMN6TP STMicroelectronics, M95320-DRMN6TP Datasheet - Page 30
M95320-DRMN6TP
Manufacturer Part Number
M95320-DRMN6TP
Description
EEPROM 32Kb SPI bus EEPROM 20 MHz 4kB
Manufacturer
STMicroelectronics
Datasheet
1.M95320-RMC6TG.pdf
(46 pages)
Specifications of M95320-DRMN6TP
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Power-up and delivery state
7
7.1
7.2
30/46
Power-up and delivery state
Power-up state
After power-up, the device is in the following state:
●
●
●
●
●
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
Standby power mode,
deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
not in the Hold condition,
the Write Enable Latch (WEL) is reset to 0,
Write In Progress (WIP) is reset to 0.
Doc ID 5711 Rev 15
M95320-W M95320-R M95320-DF
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