ATAES132-MA3H-ER-T Atmel, ATAES132-MA3H-ER-T Datasheet - Page 154
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ATAES132-MA3H-ER-T
Manufacturer Part Number
ATAES132-MA3H-ER-T
Description
EEPROM AES 32Kbit (MA3) I2C
Manufacturer
Atmel
Datasheet
1.ATAES132-SH-EQ.pdf
(166 pages)
Specifications of ATAES132-MA3H-ER-T
Rohs
yes
Maximum Clock Frequency
1 MHz
Operating Supply Voltage
6 V
Maximum Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
UDFN-8
Interface Type
I2C
Factory Pack Quantity
5000
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P.1.5. Read Operations
P.1.6. Read Protect
P.1.7. Standby Mode
P.1.8. Operating Voltage
P.2.
P.2.1. Package Pins
P.2.2. Write Protect (
Reading beyond the end of physical memory on the AT24C32C causes the internal data address register to rollover to
address zero. The read operation continues from address zero.
If an ATAES132 read operation begins at a valid user memory address but continues past the end of user memory, the read
operation will not wrap to the beginning of user memory. Reading beyond the end of user memory causes 0xFF to be
returned to the host in reply to the read, the internal data address register stops incrementing, and an error bit is set in the
STATUS register (see Section G.2.5).
The AT24C32C and other standard I
On the ATAES132, the user memory read permissions are controlled by the ZoneConfig Registers (see Section E.2.22). The
user memory is divided into 16 user zones which are independently controlled by 16 ZoneConfig Registers – different read
permissions can be assigned to different sections of the memory. If read access is prohibited, then 0xFF will be returned to
the host in reply to a read command (see Section 5.2). By default all user memory has open read access.
Standard I
The ATAES132 has three powered states: the active state and two low power states, the standby state and the sleep state.
The ATAES132 will remain in the active state between operations unless the host sends a sleep command to activate the
standby state or the sleep state. The ATAES132 can also be configured to automatically enter a low power state at power up.
See Appendix L for details on the power management features.
The AT24C32C operating voltage range is 1.8V minimum to 5.5 Vmaximum.
The ATAES132 operating voltage range is 2.5V minimum to 5.5 Vmaximum. See Section 9.3 for DC specifications.
SPI Serial EEPROM Compatibility
This section describes differences between the AT25320B standard Atmel 32K bit SPI Serial EEPROM and the ATAES132
Secure Serial EEPROM configured for SPI communication mode.
On AT25320B pin three is the
On ATAES132 pins three and seven are not used in SPI communication mode – these pins can be tied to V
state of these two pins with no impact on the functionality of the ATAES132 in the SPI communication mode. See Section K.2
for the pin descriptions.
The AT25320B
write operations are allowed. The write protect pin can be disabled by writing the WPEN bit in the STATUS register to 0b.
On the ATAES132, the user memory write permissions are controlled by the ZoneConfig Registers (see Section E.2.22). The
user memory is divided into 16 user zones which are independently controlled by 16 ZoneConfig Registers – different write
permissions can be assigned to different sections of the memory. By default, all user memory has open write access.
2
C EEPROM automatically enter low power standby mode upon completion of any internal operation.
)
input pin inhibits all EEPROM write operations when the WP pin is low. If WP is high, then EEPROM
2
C EEPROM do not have a read inhibit function.
input, and pin seven is the
Atmel ATAES132 Preliminary Datasheet
input.
8760A−CRYPTO−5/11
CC
or V
SS
. The
154
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