LFE3-150EA-7LFN672C Lattice, LFE3-150EA-7LFN672C Datasheet - Page 88
LFE3-150EA-7LFN672C
Manufacturer Part Number
LFE3-150EA-7LFN672C
Description
FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-150EA-7LFN672C
Rohs
yes
Number Of Gates
149 K
Number Of Logic Blocks
372
Embedded Block Ram - Ebr
6850 Kbit
Number Of I/os
380
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-672
Distributed Ram
303 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
219.5 mA
Factory Pack Quantity
40
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-7LFN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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DLL Timing
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
Parameter
REF
FB
CLKOP
CLKOS
PJIT
DUTY
DUTYTRD
DUTYCIR
SKEW
PHASE
PWH
PWL
INSTB
LOCK
RSWD
DEL
RANGE1
RANGE4
3
1
2
Input reference clock frequency (on-chip or
off-chip)
Feedback clock frequency (on-chip or off-chip)
Output clock frequency, CLKOP
Output clock frequency, CLKOS
Output clock period jitter (clean input)
Output clock duty cycle (at 50% levels, 50% duty
cycle input clock, 50% duty cycle circuit turned
off, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary
duty cycle input clock, 50% duty cycle circuit
enabled, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary
duty cycle input clock, 50% duty cycle circuit
enabled, clock injection removal mode) with DLL
cascading
Output clock to clock skew between two outputs
with the same phase setting
Phase error measured at device pads between
off-chip reference clock and feedback clocks
Input clock minimum pulse width high (at 80%
level)
Input clock minimum pulse width low (at 20%
level)
Input clock period jitter
DLL lock time
Digital reset minimum pulse width (at 80% level)
Delay step size
Max. delay setting for single delay block
(64 taps)
Max. delay setting for four chained delay blocks
Description
Over Recommended Operating Conditions
3-35
Edge Clock
Primary Clock
Primary Clock < 250MHz
Primary Clock 250MHz
Edge Clock
Primary Clock < 250MHz
Primary Clock 250MHz
Edge Clock
Condition
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
Min.
33.3
133
133
133
550
550
1.9
7.6
40
30
45
30
45
40
30
45
27
—
—
—
8
3
Typ.
12.4
3.1
45
—
—
—
—
—
—
—
—
—
—
—
—
+/-400
Max.
8200
17.6
500
500
500
500
200
100
500
4.4
60
70
55
70
55
60
70
55
70
—
—
—
ps p-p
cycles
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ns
ps
ns
ns
%
%
%
%
%
%
%
%
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