LCMXO2-256HC-4TG100C Lattice, LCMXO2-256HC-4TG100C Datasheet - Page 22
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LCMXO2-256HC-4TG100C
Manufacturer Part Number
LCMXO2-256HC-4TG100C
Description
FPGA - Field Programmable Gate Array 256 LUTs 56 I/O 3.3V 4 SPEED
Manufacturer
Lattice
Datasheet
1.LCMXO2280E-4BN256C.pdf
(30 pages)
Specifications of LCMXO2-256HC-4TG100C
Rohs
yes
Number Of Gates
256
Embedded Block Ram - Ebr
0 Kbit
Number Of I/os
56
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Distributed Ram
2 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
1.15 mA
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-256HC-4TG100C
Manufacturer:
MAXIM
Quantity:
101
Company:
Part Number:
LCMXO2-256HC-4TG100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
4.1 MachXO2 Product Family Surface Mount Preconditioning Testing
The Surface Mount Preconditioning (SMPC) Test is used to model the surface mount assembly conditions
during component solder processing. All devices stressed through Temperature Cycling, Un-biased HAST and
Biased HAST were preconditioned. This preconditioning is consistent with JEDEC JESD22-A113F
“Preconditioning Procedures of Plastic Surface Mount Devices Prior to Reliability Testing”, Moisture Sensitivity
Level 3 (MSL3) package moisture sensitivity and dry-pack storage requirements.
Surface Mount Preconditioning (MSL3)
(10 Temperature Cycles, 24 hours bake @ 125°C, 30°C/60% RH, soak 192 hours, 260°C Reflow Simulation, 3
passes) performed before all package tests.
MSL3 Packages: TQFP, μcBGA, csBGA, caBGA, ftBGA, fpBGA and QFN
Method: Lattice Procedure # 70-103467, J-STD-020D.1 and JESD22-A113F
Table 4.1.1 Surface Mount Precondition Data
* 6 units had 1 corner solder ball knocked off
** 1 unit failed for “package damage “due to handling damage.
INDEX Return
Product Name
due to handling damage. Sample size reduced
accordingly for each of three assembly lots.
LCMXO2-1200
LCMXO2-1200
LCMXO2-1200
LCMXO2-4000
LCMXO2-4000
LCMXO2-4000
LCMXO2-7000
LCMXO2-7000
LCMXO2-1200
LCMXO2-1200
LCMXO2-1200
LCMXO2-7000
LCMXO2-7000
LCMXO2-7000
LCMXO2-7000
LCMXO2-7000
Sample size reduced by one.
LCMXO2-256
LCMXO2-256
LCMXO2-256
LCMXO2-256
LCMXO2-256
132csBGA
132csBGA
132csBGA
184csBGA
184csBGA
184csBGA
332caBGA
332caBGA
484fpBGA
484fpBGA
484fpBGA
64ucBGA
64ucBGA
144TQFP
144TQFP
144TQFP
144TQFP
144TQFP
Package
32-QFN
32-QFN
32-QFN
Assembly
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
ASEM
Site
Lot Number
Lot #1
Lot #2
Lot #3
Lot #1
Lot #2
Lot #1
Lot #2
Lot #3
Lot #1
Lot #2
Lot #3
Lot #1
Lot #2
Lot #1
Lot #2
Lot #3
Lot #1
Lot #2
Lot #1
Lot #2
Lot #3
22
MachXO2 Cumulative SMPC Failure Rate = 0 / 4,914
Quantity
245**
307*
306*
305*
246
246
169
169
308
308
308
255
255
255
308
308
308
77
77
77
77
Lattice Semiconductor Corporation Doc. #25-106923 Rev. F
# of Fails
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Temperature
Reflow
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
250°C
250°C
250°C
260
260
260
C
C
C