PCI-MT64-O4-N1 Lattice, PCI-MT64-O4-N1 Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
PCI-MT64-O4-N1
Manufacturer Part Number
PCI-MT64-O4-N1
Description
FPGA - Field Programmable Gate Array PCI Master/Target 64B
Manufacturer
Lattice
Datasheet
1.PCI-MT32-O4-N2.pdf
(193 pages)
Specifications of PCI-MT64-O4-N1
Factory Pack Quantity
1
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Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-12. 32-bit Master Single Write Transaction with a 64-bit Local Interface
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
lm_64bit_transn
lm_cben_in[3:0]
lm_cben_in[7:4]
lm_hdata_xfern
lm_ldata_xfern
l_ad_in[63:32]
lm_status[3:0]
l_ad_in[31:0]
lm_req64n
ad[63:32]
cben[3:0]
cben[7:4]
ad[31:0]
devseln
lm_gntn
lm_rdyn
framen
ack64n
req64n
par64
irdyn
trdyn
reqn
gntn
par
clk
1
2
Termination
Bus
3
Bus Length
Don’t care
Command
Don’t care
Don’t care
Address
( = 1 )
Bus
4
5
Don’t care
Don’t care
Address
Loading
Don’t care
Don’t care
Don’t care
6
44
Command
Don’t care
Address
Enable 1
Enable 2
Data 1
Data 2
Bus
Byte
Byte
Bus Length
7
( = 1 )
Enable 2
Address
Parity
Byte
8
Byte Enable 1
Transaction
Data 1
Data 2
Bus
Don’t care
9
2
Don’t care
Don’t care
Parity 1
Data
Don’t care
Don’t care
Don’t care
Don’t care
10
Don’t care
Enable 2
Data 2
Byte
Functional Description
1
11
PCI IP Core User’s Guide
Parity 2
Data
Termination
Termination
12
Normal
Bus
0
13
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