LCMXO2-4000HC-5BG332C Lattice, LCMXO2-4000HC-5BG332C Datasheet - Page 59
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LCMXO2-4000HC-5BG332C
Manufacturer Part Number
LCMXO2-4000HC-5BG332C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 275 IO 3.3V 5 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000HC-5BG332C
Rohs
yes
Maximum Operating Frequency
133 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
BGA-332
Minimum Operating Temperature
0 C
Operating Supply Current
128 uA
Factory Pack Quantity
119
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000HC-5BG332C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered
Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned
t
t
f
f
f
Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered
t
t
f
f
f
7:1 LVDS Inputs (GDDR71_RX.ECLK.7:1)
t
t
f
f
f
Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned
t
t
f
f
t
t
f
f
Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned
t
t
f
f
f
DVA
DVE
DATA
DDRX4
SCLK
SU
HO
DATA
DDRX4
SCLK
DVA
DVE
DATA
DDR71
CLKIN
DIA
DIB
DATA
DDRX1
DVB
DVA
DATA
DDRX1
DIA
DIB
DATA
DDRX2
SCLK
Parameter
Input Data Valid After ECLK
Input Data Hold After ECLK
DDRX4 Serial Input Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
Input Data Setup Before ECLK
Input Data Hold After ECLK
DDRX4 Serial Input Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
Input Data Valid After ECLK
Input Data Hold After ECLK
DDR71 Serial Input Data
Speed
DDR71 ECLK Frequency
7:1 Input Clock Frequency
(SCLK) (minimum limited by
PLL)
Output Data Invalid After CLK
Output
Output Data Invalid Before
CLK Output
DDRX1 Output Data Speed
DDRX1 SCLK frequency
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDRX1 Output Data Speed
DDRX1 SCLK Frequency
(minimum limited by PLL)
Output Data Invalid After CLK
Output
Output Data Invalid Before
CLK Output
DDRX2 Serial Output Data
Speed
DDRX2 ECLK frequency
SCLK Frequency
Description
9
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
MachXO2-640U,
MachXO2-1200/U and
larger devices, bottom
side only
All MachXO2 devices,
all sides
All MachXO2 devices,
all sides
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
Device
3-20
0.739
0.233
0.287
0.739
1.210
1.210
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
DC and Switching Characteristics
0.290
0.290
0.520
0.520
0.200
0.200
Max.
756
378
756
378
756
378
108
300
150
300
150
664
332
166
95
95
—
—
—
—
—
—
MachXO2 Family Data Sheet
0.699
0.219
0.287
0.699
1.510
1.510
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
0.320
0.320
0.550
0.550
0.215
0.215
Max.
630
315
630
315
630
315
250
125
250
125
554
277
139
79
79
90
—
—
—
—
—
—
0.703
0.198
0.344
0.703
1.870
1.870
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-4
0.345
0.345
0.580
0.580
0.230
0.230
Max.
524
262
524
262
524
262
208
208
462
104
104
231
116
66
66
75
—
—
—
—
—
—
Units
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
UI
UI
UI
UI
9
9
9
9
9