LCMXO2-4000HE-5FTG256I Lattice, LCMXO2-4000HE-5FTG256I Datasheet - Page 20
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO2-4000HE-5FTG256I
Manufacturer Part Number
LCMXO2-4000HE-5FTG256I
Description
FPGA - Field Programmable Gate Array 4320 LUTs 207 IO 1.2V 5 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000HE-5FTG256I
Rohs
yes
Maximum Operating Frequency
133 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-256
Minimum Operating Temperature
- 40 C
Operating Supply Current
128 uA
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000HE-5FTG256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 20 of 106
- Download datasheet (8Mb)
Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges)
Right Edge
The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In
addition to the modes described above, the input register block on the right edge also supports DDR memory
mode.
In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modi-
fied DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data
streams are synchronized to the system clock to generate two data streams.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and
DDRCLKPOL signals are generated in the DQS read-write block.
Figure 2-13. MachXO2 Input Register Block Diagram (PIO on Right Edge)
Output Register Block
The output register block registers signals from the core of the device before they are passed to the sysIO buffers.
Left, Top, Bottom Edges
In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type
register or latch.
DQSR90
SCLK
D
SCLK
D
Programmable
Delay Cell
Programmable
Delay Cell
D
DDRCLKPOL
Q
Q0
D
D
Q
Q
D
Q0
Q1
2-16
Q
Q1
D
D
Q
Q
S1
S0
D
D
MachXO2 Family Data Sheet
Q
Q
D/L Q
D
Q
INDD
INCK
D/L Q
D
Q
INCK
INDD
Q1
Q0
Architecture
Q1
Q0
Related parts for LCMXO2-4000HE-5FTG256I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LCMXO2-4000HE-4BG332C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 275 IO 1.2V 4 Spd
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4BG256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 207 IO 1.2V 4 Spd
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4MG132C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 105 IO 1.2V 4 Spd
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4FG484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 279 IO 1.2V 4 Spd
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4FTG256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 207 IO 1.2V 4 Spd
Manufacturer:
Lattice
![LCMXO2-4000HE-4TG144C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 115 IO 1.2V 4 Spd
Manufacturer:
Lattice
![LCMXO2-4000HE-5MG184I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -5 Speed, IND
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-6MG184C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -6 Speed, COM
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4MG184I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -4 Speed, IND
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-6MG184I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -6 Speed, IND
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4MG184C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -4 Speed, COM
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-5MG184C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -5 Speed, COM
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4FTG256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 207 IO 1.2V 4 Spd
Manufacturer:
Lattice
Datasheet:
![LCMXO2-4000HE-4BG256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 207 IO 1.2V 4 Spd
Manufacturer:
Lattice
![LCMXO2-4000HE-6MG132C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 4320 LUTs 105 IO 1.2V 6 Spd
Manufacturer:
Lattice
Datasheet: