LFE3-35EA-7LFTN256I Lattice, LFE3-35EA-7LFTN256I Datasheet - Page 107
LFE3-35EA-7LFTN256I
Manufacturer Part Number
LFE3-35EA-7LFTN256I
Description
FPGA - Field Programmable Gate Array 33.3K LUTs 133 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-35EA-7LFTN256I
Rohs
yes
Factory Pack Quantity
90
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-7LFTN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 3-21. sysCONFIG Parallel Port Write Cycle
Figure 3-22. sysCONFIG Master Serial Port Timing
Figure 3-23. sysCONFIG Slave Serial Port Timing
WRITEN
1. In Master Parallel Mode the FPGA provides CCLK (MCLK). In Slave Parallel Mode the external device provides CCLK.
CCLK (output)
CCLK (input)
CCLK
CS1N
BUSY
D[0:7]
CSN
DOUT
1
DOUT
DIN
DIN
t
SUCBDI
t
t
SUWD
SUCS
Byte 0
t
t
SUSCDI
SUMCDI
t
BSCL
Byte 1
t
HCBDI
3-54
t
SSCL
Byte 2
t
DCB
t
BSCYC
t
BSCH
DC and Switching Characteristics
t
t
CODO
CODO
LatticeECP3 Family Data Sheet
t
SSCH
Byte n
t
t
HSCDI
HMCDI
t
HCS
t
HWD
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