LFE2-6E-5T144I Lattice, LFE2-6E-5T144I Datasheet - Page 13

• Manufacturer Part Number: LFE2-6E-5T144I
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -5 I
• Manufacturer: Lattice

Specifications of LFE2-6E-5T144I

• Number Of I/os: 90
• Maximum Operating Frequency: 311 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 300

Lattice Semiconductor
clock distribution network. The Reset (RST) control signal resets input and synchronously forces all outputs to low.
The RELEASE signal releases outputs synchronously to the input clock. For further information on clock dividers,
please see details of additional technical documentation at the end of this data sheet. Figure 2-7 shows the clock
divider connections.
Figure 2-7. Clock Divider Connections
Clock Distribution Network
LatticeECP2 devices have eight quadrant-based primary clocks and eight flexible region-based secondary clocks/
control signals. Two high performance edge clocks are available on each edge of the device to support high speed
interfaces. These clock inputs are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock
inputs are fed throughout the chip via a clock distribution system.
Primary Clock Sources
LatticeECP2 devices derive clocks from five primary sources: PLL (GPLL and SPLL) outputs, DLL outputs,
CLKDIV outputs, dedicated clock inputs and routing. LatticeECP2 devices have two to six sysCLOCK PLLs and
two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side
of the device. Figure 2-8 shows the primary clock sources.
CLKOP (GPLL)
CLKOS (GPLL)
CLKOP (DLL)
CLKOS (DLL)
CLKINDEL
PLL PAD
Routing
RELEASE
RST
2-10
CLKDIV
LatticeECP2 Family Data Sheet
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÷2
÷4
÷8
Architecture