LFE2-6E-5T144C Lattice, LFE2-6E-5T144C Datasheet - Page 39

• Manufacturer Part Number: LFE2-6E-5T144C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -5
• Manufacturer: Lattice

Specifications of LFE2-6E-5T144C

• Number Of I/os: 90
• Maximum Operating Frequency: 311 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-144
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 300

Lattice Semiconductor
Figure 2-33. DQS Local Bus
Polarity Control Logic
In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown.
The LatticeECP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and
hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
DQSXFER
DQS
DQS
DCNTL[6:0]
ECLK1
DQSXFER
DCNTL[6:0]
CLK1
GSR
DQS
CEI
2-36
Polarity Control
DQSXFERDEL*
To DDR
Register Block
Register Block
PIO
PIO
Reg.
DQSDEL
Logic
Output
Input
To Sync
Reg.
Calibration bus
from DLL
LatticeECP2 Family Data Sheet
Buffer
Buffer
sysIO
sysIO
DI
DI
Strobe
Datain
DDR
DQS
PAD
PAD
Architecture