LFE2-50E-5F484C Lattice, LFE2-50E-5F484C Datasheet - Page 22
LFE2-50E-5F484C
Manufacturer Part Number
LFE2-50E-5F484C
Description
FPGA - Field Programmable Gate Array 48K LUTs 339 I/O DSP 1.2V 5SPD
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-50E-5F484C
Number Of I/os
339
Maximum Operating Frequency
311 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-484
Minimum Operating Temperature
0 C
Factory Pack Quantity
300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-50E-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-18. Memory Core Reset
For further information on the sysMEM EBR block, please see the details of additional technical documentation at
the end of this data sheet.
sysDSP™ Block
The LatticeECP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Sig-
nal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR)
filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP2, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-19 compares the fully serial and
the mixed parallel and serial implementations.
GSRN
RSTA
RSTB
Programmable Disable
Memory Core
2-19
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeECP2 Family Data Sheet
Port A[17:0]
Port B[17:0]
Architecture
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