5CSEBA5U19C6N Altera Corporation, 5CSEBA5U19C6N Datasheet - Page 3

• Manufacturer Part Number: 5CSEBA5U19C6N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 3207 LABs 66 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA5U19C6N

• Rohs: yes
• Number Of Logic Blocks: 3207
• Embedded Block Ram - Ebr: 480 kbit
• Number Of I/os: 66
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-484
• Distributed Ram: 3970 kbit
• Minimum Operating Temperature: 0 C

CV-51001
2012.12.28
Cyclone V Device Overview
Cyclone V Device Variants and Packages
Table 3: Device Variants for the Cyclone V Device Family
and ST devices only)
(Cyclone V SE, SX,
Configuration
Cyclone V GX
Cyclone V GT
Cyclone V SX
Cyclone V ST
Cyclone V SE
Cyclone V E
Feature
Variant
HPS
Optimized for the lowest system cost and power requirement for a wide spectrum of
general logic and DSP applications
Optimized for the lowest cost and power requirement for 614 Mbps to 3.125 Gbps
transceiver applications
The FPGA industry’s lowest cost and lowest power requirement for 5 Gbps transceiver
applications
SoC FPGA with integrated ARM-based HPS
SoC FPGA with integrated ARM-based HPS and 3.125 Gbps transceivers
SoC FPGA with integrated ARM-based HPS and 5 Gbps transceivers
Single or dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximum
frequency with support for symmetric and asymmetric multiprocessing
Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0
On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller,
NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART,
controller area network (CAN), serial peripheral interface (SPI), I2C interface, and
up to 85 HPS GPIO interfaces
System peripherals—general-purpose timers, watchdog timers, direct memory access
(DMA) controller, FPGA configuration manager, and clock and reset managers
On-chip RAM and boot ROM
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight
HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in
the HPS, and vice versa
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to
the multiport front end (MPFE) of the HPS SDRAM controller
ARM CoreSight
Tamper protection—comprehensive design protection to protect your valuable IP
investments
Enhanced advanced encryption standard (AES) design security features
CvP
Partial and dynamic reconfiguration of the FPGA
Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP)
x8 and x16 configuration options
™
JTAG debug access port, trace port, and on-chip trace storage
Description
Description
Cyclone V Device Overview
Altera Corporation
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