5CSEBA6U19C7N Altera Corporation, 5CSEBA6U19C7N Datasheet - Page 28

• Manufacturer Part Number: 5CSEBA6U19C7N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 4150 LABs 66 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA6U19C7N

• Rohs: yes
• Number Of Logic Blocks: 4150
• Embedded Block Ram - Ebr: 621 kbit
• Number Of I/os: 66
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-484
• Distributed Ram: 5140 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
28
Power Management
Document Revision History
CvP (PCIe)
JTAG
December 2012
Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using
CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP
block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active time
requirement.
For more information about CvP, refer to the
FPGAs User
Leveraging the FPGA architectural features, process technology advancements, and transceivers that are
designed for power efficiency, the Cyclone V devices consume less power than previous generation Cyclone
FPGAs:
Additionally, Cyclone V devices contain several hard IP blocks that reduce logic resources and deliver
substantial power savings of up to 25% less power than equivalent soft implementations.
Cyclone V Device Overview
Total device core power consumption—less by up to 40%.
Transceiver channel power consumption—less by up to 50%.
Date
Mode
Guide.
2012.12.28
Version
and x4
x1, x2,
Width
lanes
Data
1 bit
Max Clock
(MHz)
Rate
33
—
Updated the pin counts for the MBGA packages.
Updated the GPIO and transceiver counts for the MBGA packages.
Updated the GPIO counts for the U484 package of the Cyclone V E
A9, GX C9, and GT D9 devices.
Updated the vertical migration table for vertical migration of the U484
packages.
Updated the MLAB supported programmable widths at 32 bits depth.
Max Data
(Mbps)
Rate
—
33
Configuration via Protocol (CvP) Implementation in Altera
Decompres-
sion
—
—
Changes
Design Se-
curity
Yes
—
Partial Recon-
figuration
Cyclone V Device Overview
—
—
Remote Sys-
tem Update
—
—
2012.12.28
CV-51001