5AGXMA1D4F27C4N Altera Corporation, 5AGXMA1D4F27C4N Datasheet - Page 25
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5AGXMA1D4F27C4N
Manufacturer Part Number
5AGXMA1D4F27C4N
Description
FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 336 IOs
Manufacturer
Altera Corporation
Series
Arria V GXr
Datasheet
1.5AGXFB3H4F40C5N.pdf
(33 pages)
Specifications of 5AGXMA1D4F27C4N
Rohs
yes
Number Of Logic Blocks
2830
Number Of I/os
336
Maximum Operating Frequency
800 MHz
Operating Supply Voltage
1.2 V to 1.8 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
FBGA-672
Distributed Ram
8463 kbit
Minimum Operating Temperature
0 C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5AGXMA1D4F27C4N
Manufacturer:
FSC
Quantity:
1 001
AV-51001
2013.01.11
Arria V Device Overview
22
23
24
25
26
27
Table 21: Transceiver PCS Features for Arria V GX, GT, ST, and SX Devices
Custom single- and
double-width modes
SRIO
Serial ATA
PCIe Gen1
(x1, x2, x4, x8)
PCIe Gen2
(x1, x2, x4)
GbE
XAUI
SDI
GPON
CPRI
Data rates above 6.5536 Gbps up to 10.3125 Gbps, such as 10GBASE-R, are supported through the soft PCS.
PCIe Gen2 is supported only through the PCIe hard IP.
XAUI is supported through the soft PCS.
The 0.27 Gbps data rate is supported using oversampling user logic that you must implement in the FPGA
fabric.
The GPON standard does not support burst mode.
CPRI data rates above 6.5536 Gbps, such as 9.8304 Gbps, are supported through the soft PCS.
PCS Support
27
24
26
23
22
0.6144 to 6.144
0.27
1.25 and 2.5
1.25 to 6.25
1.5, 3.0, 6.0
2.5 and 5.0
Data Rates
0.611 to
~6.5536
(Gbps)
3.125
25
1.25
2.97
, 1.485,
Transmitter Data Path Feature
Phase compensation FIFO
Byte serializer
8B/10B encoder
Phase compensation FIFO
Byte serializer
8B/10B encoder
PIPE 2.0 interface to the core
logic
Phase compensation FIFO
Byte serializer
8B/10B encoder
Phase compensation FIFO
Byte serializer
8B/10B encoder
XAUI state machine for
bonding four channels
Phase compensation FIFO
Byte serializer
Phase compensation FIFO
Byte serializer
8B/10B encoder
TX deterministic latency
Arria V Device Overview
Receiver Data Path Feature
Word aligner
8B/10B decoder
Byte deserializer
Phase compensation FIFO
Word aligner
8B/10B decoder
Byte deserializer
Phase compensation FIFO
Rate match FIFO
PIPE 2.0 interface to the core
logic
Word aligner
8B/10B decoder
Byte deserializer
Phase compensation FIFO
Rate match FIFO
Word aligner
8B/10B decoder
Byte deserializer
Phase compensation FIFO
XAUI state machine for
realigning four channels
Deskew FIFO circuitry
Byte deserializer
Phase compensation FIFO
Word aligner
8B/10B decoder
Byte deserializer
Phase compensation FIFO
RX deterministic latency
Altera Corporation
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