MC100EPT20DTG ON Semiconductor, MC100EPT20DTG Datasheet
MC100EPT20DTG
Specifications of MC100EPT20DTG
Related parts for MC100EPT20DTG
MC100EPT20DTG Summary of contents
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MC10EPT20, MC100EPT20 3.3V LVTTL/LVCMOS to Differential LVPECL Translator The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single ...
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NC 1 LVTTL LVPECL NC 4 Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack ...
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Table 3. MAXIMUM RATINGS Symbol Parameter V Power Supply CC V Input Voltage I I Output Current out TA Operating Temperature Range T Storage Temperature Range stg Thermal Resistance (Junction−to−Ambient Thermal Resistance (Junction−to−Case Thermal Resistance ...
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Table 4. LVTTL INPUT DC CHARACTERISTICS Symbol Characteristic I Input HIGH Current ( Input HIGH Current MAX (V IHH in I Input LOW Current ( Input Clamp Voltage ...
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Table 6. 100EPT PECL OUTPUT DC CHARACTERISTICS Symbol Characteristic I Positive Power Supply Current CC V Output HIGH Voltage (Note Output LOW Voltage (Note 6) OL NOTE: Device will meet the specifications after thermal equilibrium has been ...
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900 800 700 600 500 400 300 200 100 É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É ...
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... MC10EPT20DTR2 MC10EPT20DTR2G MC10EPT20MNR4 MC10EPT20MNR4G MC100EPT20D MC100EPT20DG MC100EPT20DR2 MC100EPT20DR2G MC100EPT20DT MC100EPT20DTG MC100EPT20DTR2 MC100EPT20DTR2G MC100EPT20MNR4 MC100EPT20MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D ...
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... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...
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K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...