AT6005-2QI Atmel, AT6005-2QI Datasheet - Page 19

• Manufacturer Part Number: AT6005-2QI
• Description: FPGA - Field Programmable Gate Array ASICS
• Manufacturer: Atmel

Specifications of AT6005-2QI

• Product Category: FPGA - Field Programmable Gate Array
• Number Of Gates: 15 K
• Number Of I/os: 108
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BQFP-132
• Minimum Operating Temperature: - 40 C

AC Timing Characteristics – 5V Operation
Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds.
Worst case: V
Notes:
Cell Function
Wire
NAND
XOR
AND
MUX
D-Flip-flop
D-Flip-flop
D-Flip-flop
Bus Driver
Repeater
Column Clock
Column Reset
Clock Buffer
Reset Buffer
TTL Input
CMOS Input
Fast Output
Slow Output
Output Disable
Fast Enable
Slow Enable
Device
Cell
Bus
Column Clock
(6)
(6)
(4)
1. TTL buffer delays are measured from a V
2. CMOS buffer delays are measured from a V
3. Buffer delay is to a pad voltage of 1.5V with one output switching.
4. Max specifications are the average of mas t
5. Parameter based on characterization and simulation; not tested in production
6. Exact power calculation is available in an Atmel application note.
7. Load Definition: 1 = Load of one A or B input; 2 = Load of one L input; 3 = Constant Load; 4 = Tester Load of 50 pF.
(1)
(5)
(5)
(3)
(3)(5)
(5)
(3)
(5)
(2)
(3)(5)
(6)
CC
(5)
= 4.75V to 5.25V. Temperature = 0 C to 70 C.
= Preliminary Information
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PD
PD
PD
PD
PD
setup
hold
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PXZ
PXZ
PXZ
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(max)
(min)
(max)
(max)
(max)
(min)
(4)
Cell Types
Wire, XWire, Half-adder, Flip-flop
Wire, XWire, Half-adder, Flip-flop, Repeater
Column Clock Driver
GRES, A, EN
GCLK, A, ES
CLOCK PIN
RESET PIN
A, B, L
A, B, L
A, B, L
A, B, L
A, B, L
From
A, B
CLK
CLK
L, E
L, E
I/O
I/O
A
A
A
L
L
L
L
IH
of 1.5V at the pad to the internal V
PDLH
IH
of 1/2 V
and t
I/O PIN
I/O PIN
I/O PIN
I/O PIN
I/O PIN
A, B, L
GRES
GCLK
CLK
CLK
RES
A, B
To
B
A
B
A
A
A
E
A
A
PDHL
L
L
CC
at the apd to the internal V
.
Definition
Load
1
1
1
1
1
1
1
2
3
2
3
3
3
3
4
4
4
4
4
-
-
-
-
(7)
IH
Outputs
at A. The input buffer load is constant.
AT6000(LV) Series
A, B
CLK
L
0.8
1.6
1.8
1.7
1.7
2.1
1.5
1.5
2.0
1.3
1.7
1.8
1.8
1.6
1.5
1.0
1.3
3.3
7.5
3.1
3.8
8.2
IH
-1
0
at A. The input buffer load is constant.
1.2
2.2
2.4
2.2
2.3
3.0
2.0
2.0
2.6
1.6
2.1
2.4
2.4
2.0
1.9
1.2
1.4
3.5
8.0
3.3
4.0
8.5
-2
0
4.5 µA/MHz
2.5 µA/MHz
40 µA/MHz
12.0
12.5
I
1.8
3.2
4.0
3.2
4.0
4.9
3.0
3.0
4.0
2.3
3.0
3.0
3.0
2.9
2.8
1.5
2.3
6.0
5.5
6.5
CC
-4
0
(max)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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