LFX125C-03FN256C Lattice, LFX125C-03FN256C Datasheet - Page 12
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LFX125C-03FN256C
Manufacturer Part Number
LFX125C-03FN256C
Description
FPGA - Field Programmable Gate Array 139K Gt ispJTAG 1.8V -3 Spd
Manufacturer
Lattice
Datasheet
1.LFX125EB-04F256C.pdf
(115 pages)
Specifications of LFX125C-03FN256C
Product Category
FPGA - Field Programmable Gate Array
Rohs
yes
Number Of Gates
139 K
Number Of I/os
160
Operating Supply Voltage
1.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-256
Minimum Operating Temperature
0 C
Factory Pack Quantity
450
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Lattice Semiconductor
Memory
The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded
Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see Look-
Up Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM
or ROM. Additionally, the internal logic of the device can be used to configure the memory elements as FIFO and
other storage types. These EBRs are referred to as sysMEM blocks. Refer to Table 1 for memory resources per
device.
sysMEM Blocks
The sysMEM blocks are organized in columns distributed throughout the device. Each EBR contains 4.6K bits of
dual-port RAM with dedicated control, address, and data lines for each port. Each column of sysMEM blocks has
dedicated address and control lines that can be used by each block separately or cascaded to form larger memory
elements. The memory cells are symmetrical and contain two sets of identical control signals. Each port has a
read/write clock, clock enable, write enable, and output enable. Figure 12 illustrates the sysMEM block.
The ispXPGA memory block can operate as single-port or dual-port RAM. Supported configurations are:
The data widths of “9” and “18” are ideal for applications where parity is necessary. This allows 9 data bits, 8 data
bits plus a parity bit, 18 data bits, or 16 data bits plus two parity bits. The logic for generating and checking the par-
ity must be customized separately.
Figure 12. sysMEM Block Diagram
Read and Write Operations
The ispXPGA EBR has fully synchronous read and write operations as well as an asynchronous read operation.
These operations allow several different types of memory to be implemented in the device.
Synchronous Read: The Clock Enable (CE) and Write Enable (WE) signals control the synchronous read opera-
tion. When the CE signal is low, the clock is enabled. When the WE signal is low the read operation begins. Once
the address (ADDR) is present, a rising clock edge (or falling edge depending on polarity) causes the stored data
to be available on the DATA port. Figure 13 illustrates the synchronous read timing.
• 512 x 9 bits single-port
• 256 x 18 bits single-port
• 512 x 9 bits dual-port
• 256 x18 bits dual-port
ADDRA
DATAA
CLKA
WEA
CEA
OEA
(8 bits data / 1 bit parity)
(16 bits data / 2 bits parity)
(8 bits data / 1 bit parity)
(16 bits data / 2 bits parity)
sysMEM Block
12
ispXPGA Family Data Sheet
ADDRB
WEB
DATAB
OEB
CLKB
CEB
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