MC100EP91DWG ON Semiconductor, MC100EP91DWG Datasheet - Page 7

• Manufacturer Part Number: MC100EP91DWG
• Description: TRANSLATOR NECL OUTPUT 20-SOIC
• Manufacturer: ON Semiconductor
• Series: 100EPr

Specifications of MC100EP91DWG

• Logic Function: Translator
• Number Of Bits: 3
• Input Type: AnyLevel™
• Output Type: NECL
• Number Of Channels: 3
• Number Of Outputs/channel: 1
• Differential - Input:output: Yes/Yes
• Propagation Delay (max): 0.675ns
• Voltage - Supply: 2.375 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Supply Voltage: 2.375 V ~ 3.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -

Application Information
LVCMOS, HSTL, CML, or LVDS signal levels. The
limitations for differential input signal (LVDS, HSTL,
LVPECL, or CML) are the minimum input swing of 150 mV
All MC100EP91 inputs can accept LVPECL, LVTTL,
LVPECL
LVTTL
Driver
HSTL
Driver
Driver
GND
GND
GND
V
V
V
CC
CC
CC
Figure 6. Standard LVPECL Interface
Figure 10. Standard LVTTL Interface
Figure 8. Standard HSTL Interface
(externally generated
reference voltage)
Z
Z
Z
Z
V
TT
= V
1.5 V
50 W
50 W
GND
Z
CC
− 2.0 V
50 W
50 W
D
D
D
D
D
D
GND
GND
GND
EP91
EP91
EP91
V
V
V
CC
CC
CC
V
V
V
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EE
EE
EE
7
and the maximum input swing of 3.0 V. Within these
conditions, the input voltage can range from V
Examples interfaces are illustrated below in a 50 W
environment (Z = 50 W)
LVCMOS
LVDS
Driver
Driver
Driver
CML
GND
GND
GND
V
V
V
A reference voltage of V
CC
CC
CC
to D input, if D is interfaced to CMOS signals.)
Figure 9. Standard 50 W Load CML Interface
Figure 7. Standard LVDS Interface
(D will default to V
Figure 11. Standard LVCMOS Interface
Z
Z
Z
Z
100 W
Open
50 W
Z
V
CC
CC
CC
/2 when left open.
50 W
/2 should be applied
D
D
D
D
D
D
GND
GND
GND
EP91
EP91
EP91
CC
V
V
V
CC
CC
CC
to GND.
V
V
V
EE
EE
EE